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PRELIMINARY
4-MBIT (256K X 16, 512K X 8) SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
28F400BV-T/B, 28F400CV-T/B, 28F004BV-T/B 28F400CE-T/B, 28F004BE-T/B
Intel SmartVoltage Technology 5V or 12V Program/Erase 2.7V, 3.3V or 5V Read Operation Increased Programming Throughput at 12V VPP Very High-Performance Read 5V: 60/80/120 ns Max. Access Time, 30/40 ns Max. Output Enable Time 3V: 110/150/180 ns Max Access 65/90 ns Max. Output Enable Time 2.7V: 120 ns Max Access 65 ns Max. Output Enable Time Low Power Consumption Max 60 mA Read Current at 5V Max 30 mA Read Current at 2.7V-3.6V x8/x16-Selectable Input/Output Bus 28F400 for High Performance 16- or 32-bit CPUs x8-Only Input/Output Architecture 28F004B for Space-Constrained 8-bit Applications Optimized Array Blocking Architecture One 16-KB Protected Boot Block Two 8-KB Parameter Blocks One 96-KB Main Block Three 128-KB Main Blocks Top or Bottom Boot Locations Absolute Hardware-Protection for Boot Block Software EEPROM Emulation with Parameter Blocks
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Extended Temperature Operation -40C to +85C Extended Cycling Capability 100,000 Block Erase Cycles (Commercial Temperature) 10,000 Block Erase Cycles (Extended Temperature) Automated Word/Byte Program and Block Erase Industry-Standard Command User Interface Status Registers Erase Suspend Capability SRAM-Compatible Write Interface Automatic Power Savings Feature 1 mA Typical I CC Active Current in Static Operation Reset/Deep Power-Down Input 0.2 A ICCTypical Provides Reset for Boot Operations Hardware Data Protection Feature Write Lockout during Power Transitions Industry-Standard Surface Mount Packaging 40-Lead TSOP 44-Lead PSOP: JEDEC ROM Compatible 48-Lead TSOP 56-Lead TSOP Footprint Upgradeable from 2-Mbit and to 8-Mbit Boot Block Flash Memories ETOXTM IV Flash Technology
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July 1997
Order Number: 290530-005
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. The 28F400BV-T/B, 28F400CV-T/B, 28F004BV-T/B, 28F400CE-T/B, 28F004BE-T/B may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 7641 Mt. Prospect, IL 60056-7641 or call 1-800-879-4683 or visit Intel's Website at http:\\www.intel.com
COPYRIGHT (c) INTEL CORPORATION, 1997 *Third-party brands and names are the property of their respective owners. CG-041493
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PAGE 1.0 PRODUCT FAMILY OVERVIEW .................... 5 1.1 New Features in the SmartVoltage Products ..................................................... 5 1.2 Main Features.............................................. 5 1.3 Applications ................................................. 7 1.4 Pinouts......................................................... 7 1.5 Pin Descriptions......................................... 11 2.0 PRODUCT DESCRIPTION............................ 13 2.1 Memory Blocking Organization .................. 13 2.1.1 Boot Block........................................... 13 2.1.2 Parameter Blocks................................ 13 2.1.3 Main Blocks......................................... 13 3.0 PRODUCT FAMILY PRINCIPLES OF OPERATION ................................................ 15 3.1 Bus Operations .......................................... 15 3.2 Read Operations........................................ 15 3.2.1 Read Array.......................................... 15 3.2.2 Intelligent Identifiers ............................ 17 3.3 Write Operations........................................ 17 3.3.1 Command User Interface (CUI)........... 17 3.3.2 Status Register ................................... 20 3.3.3 Program Mode .................................... 21 3.3.4 Erase Mode......................................... 21 3.4 Boot Block Locking .................................... 22 3.4.1 VPP = VIL for Complete Protection ....... 22 3.4.2 WP# = VIL for Boot Block Locking ....... 22 3.4.3 RP# = VHH or WP# = VIH forr Boot Block Unlocking ........................................... 22 3.4.4 Upgrade Note for 8-Mbit 44-PSOP Package............................................. 22
4-MBIT SmartVoltage BOOT BLOCK FAMILY
CONTENTS
PAGE 3.5 Power Consumption...................................26 3.5.1 Active Power .......................................26 3.5.2 Automatic Power Savings (APS) .........26 3.5.3 Standby Power ....................................26 3.5.4 Deep Power-Down Mode.....................26 3.6 Power-Up/Down Operation.........................26 3.6.1 RP# Connected to System Reset ........26 3.6.2 VCC, VPP and RP# Transitions .............27 3.7 Power Supply Decoupling ..........................27 3.7.1 VPP Trace on Printed Circuit Boards....27 4.0 ABSOLUTE MAXIMUM RATINGS................28 5.0 COMMERCIAL OPERATING CONDITIONS .29 5.1 Applying VCC Voltages ...............................29 5.2 DC Characteristics .....................................30 5.3 AC Characteristics .....................................34 6.0 EXTENDED OPERATING CONDITIONS ......44 6.1 Applying VCC Voltages ...............................44 6.2 DC Characteristics .....................................45 6.3 AC Characteristics .....................................51 APENDIX A: Additional Information .................56 APPENDIX B: Additional Information...............57
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Description
REVISION HISTORY
Number -001 -002 Initial release of datasheet. Status changed from Product Preview to Preliminary 28F400CV/CE/BE references and information added throughout. 2.7V CE/BE specs added throughout. The following sections have been changed or rewritten: 1.1, 3.0, 3.2.1, 3.2.2, 3.3.1, 3.3.1.1, 3.3.2, 3.3.2.1, 3.3.3, 3.3.4, 3.6.2. Note 2 added to Figure 3 to clarify 28F008B pinout vs. 28F008SA. Sentence about program and erase WSM timeout deleted from Section 3.3.3, 3.3.4. Erroneous arrows leading out of error states deleted from flowcharts in Figs. 9, 10. Sections 5.1, 6.1 changed to "Applying VCC Voltages." These sections completely changed to clarify VCC ramp requirements. IPPD 3.3V Commercial spec changed from 10 to 5 A. Capacitance tables added after commercial and extended DC Characteristics tables. Test and slew rate notes added to Figs. 12, 13, 19, 20, 21. Test configuration drawings (Fig. 14, 22) consolidated into one, with component values in table. (Component values also rounded off). tELFL, tELFH, tAVFL changed from 7 to 5 ns for 3.3V BV-60 commercial and 3.3V TBV-80 extended, 10 to 5 ns for 3.3V BV-80 and BV-120 commercial. tWHAX and tEHAX changed from 10 to 0 ns. tPHWL changed from 1000 ns to 800 ns for 3.3V BV-80, BV-120 commercial. tPHEL changed from 1000 ns to 800 ns for 3.3V BV-60, BV-80, and BV-120 commercial. 28F400BE row removed from Table 1 Applying VCC voltages (Sections 5.1 and 6.1) rewritten for clarity. Minor cosmetic changes/edits. Corrections: Spec typographical error "tQWL" corrected to read "tQVVL." Intel386TM EX Microprocessor block diagram updated because latest Intel386 CPU specs require less glue logic. Spec tELFL and tELFH changed from 5 ns (max) to 0 ns (min). New specs tPLPH and tPLQX added from Specification Update document (297595). Specs tEHQZ and tGHQZ improved on most voltage/speed combinations. Correction: Appendix A, Ordering information fixed order numbers from TE27F400BVT80 to TE28F400BVT80 and TE27F400BVB80 to TE28F400BVB80. Updated disclaimer.
-003
-004
-005
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1.0
4-MBIT SmartVoltage BOOT BLOCK FAMILY
* 5V program/erase operation has been added. If switching VPP for write protection, switch to GND (not 5V) for complete write protection. To take advantage of 5V write-capability, allow for connecting 5V to VPP and disconnecting 12V from VPP line. Enhanced circuits optimize low VCC performance, allowing operation down to VCC = 2.7V (using the BE product).
PRODUCT FAMILY OVERVIEW
This datasheet contains the specifications for the two branches of products in the SmartVoltage 4-Mbit boot block flash memory family: the -BE/CE suffix products feature a low VCC operating range of 2.7V-3.6V; the -BV/CV suffix products offer 3.0V-3.6V operation. Both BE/CE and BV/CV products also operate at 5V for high-speed access times. Throughout this datasheet, the 28F400 refers to all x8/x16 4-Mbit products, while 28F004B refers to all x8 4-Mbit boot block products. Also, the term "2.7V" generally refers to the full voltage range 2.7V-3.6V. Section 1 provides an overview of the flash memory family including applications, pinouts and pin descriptions. Sections 2 and 3 describe the memory organization and operation for these products. Finally, Sections 4 and 5 contain the family's operating specifications.
*
If you are using BX/BL 12V VPP boot block products today, you should account for the differences listed above and also allow for connecting 5V to VPP and disconnecting 12V from VPP line, if 5V writes are desired.
1.2
Main Features
1.1
New Features in the SmartVoltage Products
The SmartVoltage boot block flash memory family offers identical operation with the BX/BL 12V program products, except for the differences listed below. All other functions are equivalent to current products, including signatures, write commands, and pinouts. * WP# pin has replaced a DU (Don't Use) pin. Connect the WP# pin to control signal or to VCC or GND (in this case, a logic-level signal can be placed on DU pin). See Tables 2 and 9 to see how the WP# pin works.
Intel's SmartVoltage technology is the most flexible voltage solution in the flash industry, providing two discrete voltage supply pins: VCC for read operation, and VPP for program and erase operation. Discrete supply pins allow system designers to use the optimal voltage levels for their design. The 28F400BV/CV, 28F004BV, 28F400CE and 28F004BE provide program/erase capability at 5V or 12V. The 28F400BV/CV and 28F004BV allow reads with VCC at 3.3 0.3V or 5V, while the 28F400CE and 28F004BE allow reads with VCC at 2.7V-3.6V or 5V. Since many designs read from the flash memory a large percentage of the time, read operation using the 2.7V or 3.3V ranges can provide great power savings. If read performance is an issue, however, 5V VCC provides faster read access times.
Table 1. SmartVoltage Provides Total Voltage Flexibility Product Name 28F004BV-T/B 28F400BV-T/B 28F400CV-T/B 28F004BE-T/B 28F400CE-T/B Bus Width x8 x8 or x16 x8 or x16 x8 x8 or x16 2.7V-3.6V VCC 3.3 0.3V 5V 5% 5V 10% 5V 10% VPP 12V 5%
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4-MBIT SmartVoltage BOOT BLOCK FAMILY
For program and erase operations, 5V VPP operation eliminates the need for in system voltage converters, while 12V VPP operation provides faster program and erase for situations where 12V is available, such as manufacturing or designs where 12V is in-system. For design simplicity, however, just hook up VCC and VPP to the same 5V 10% source. The 28F400/28F004B boot block flash memory family is a high-performance, 4-Mbit (4,194,304 bit) flash memory family organized as either 256 Kwords of 16 bits each (28F400 only) or 512 Kbytes of 8 bits each (28F400 and 28F004B). Separately erasable blocks, including a hardwarelockable boot block (16,384 bytes), two parameter blocks (8,192 bytes each) and main blocks (one block of 98,304 bytes and three blocks of 131,072 bytes), define the boot block flash family architecture. See Figures 7 and 8 for memory maps. Each block can be independently erased and programmed 100,000 times at commercial temperature or 10,000 times at extended temperature. The boot block is located at either the top (denoted by -T suffix) or the bottom (-B suffix) of the address map in order to accommodate different microprocessor protocols for boot code location. The hardware-lockable boot block provides complete code security for the kernel code required for system initialization. Locking and unlocking of the boot block is controlled by WP# and/or RP# (see Section 3.4 for details). The Command User Interface (CUI) serves as the interface between the microprocessor or microcontroller and the internal operation of the boot block flash memory products. The internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for program and erase operations, including verifications, thereby unburdening the microprocessor or microcontroller of these tasks. The Status Register (SR) indicates the status of the WSM and whether it successfully completed the desired program or erase operation. Program and Erase Automation allows program and erase operations to be executed using an industrystandard two-write command sequence to the CUI. Data writes are performed in word (28F400 family) or byte (28F400 or 28F004B families) increments.
Each byte or word in the flash memory can be programmed independently of other memory locations, unlike erases, which erase all locations within a block simultaneously. The 4-Mbit SmartVoltage boot block flash memory family is also designed with an Automatic Power Savings (APS) feature which minimizes system battery current drain, allowing for very low power designs. To provide even greater power savings, the boot block family includes a deep power-down mode which minimizes power consumption by turning most of the flash memory's circuitry off. This mode is controlled by the RP# pin and its usage is discussed in Section 3.5, along with other power consumption issues. Additionally, the RP# pin provides protection against unwanted command writes due to invalid system bus conditions that may occur during system reset and power-up/down sequences. For example, when the flash memory powers-up, it automatically defaults to the read array mode, but during a warm system reset, where power continues uninterrupted to the system components, the flash memory could remain in a non-read mode, such as erase. Consequently, the system Reset signal should be tied to RP# to reset the memory to normal read mode upon activation of the Reset signal. See Section 3.6. The 28F400 provides both byte-wide or word-wide input/output, which is controlled by the BYTE# pin. Please see Table 2 and Figure 16 for a detailed description of BYTE# operations, especially the usage of the DQ15/A-1 pin. The 28F400 products are available in a ROM/EPROM-compatible pinout and housed in the 44-lead PSOP (Plastic Small Outline) package, the 48-lead TSOP (Thin Small Outline, 1.2 mm thick) package and the 56-lead TSOP as shown in Figures 4, 5 and 6, respectively. The 28F004 products are available in the 40-lead TSOP package as shown in Figure 3. Refer to the DC Characteristics Table, Section 5.2 (commercial temperature) and Section 6.2 (extended temperature), for complete current and voltage specifications. Refer to the AC Characteristics Table, Section 5.3 (commercial temperature) and Section 6.3 (extended temperature), for read, write and erase performance specifications.
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1.3
4-MBIT SmartVoltage BOOT BLOCK FAMILY
The 4-Mbit flash memory products are also excellent design solutions for digital cellular phone and telecommunication switching applications requiring very low power consumption, highperformance, high-density storage capability, modular software designs, and a small form factor package. The 4-Mbit's blocking scheme allows for easy segmentation of the embedded code with 16 Kbytes of hardware-protected boot code, four main blocks of program code and two parameter blocks of 8 Kbytes each for frequently updated data storage and diagnostic messages (e.g., phone numbers, authorization codes). Intel's boot block architecture provides a flexible voltage solution for the different design needs of various applications. The asymmetrically-blocked memory map allows the integration of several memory components into a single flash device. The boot block provides a secure boot PROM; the parameter blocks can emulate EEPROM functionality for parameter store with proper software techniques; and the main blocks provide code and data storage with access times fast enough to execute code in place, decreasing RAM requirements.
Applications
The 4-Mbit boot block flash memory family combines high-density, low-power, highperformance, cost-effective flash memories with blocking and hardware protection capabilities. Their flexibility and versatility reduce costs throughout the product life cycle. Flash memory is ideal for Just-InTime production flow, reducing system inventory and costs, and eliminating component handling during the production phase. When your product is in the end-user's hands, and updates or feature enhancements become necessary, flash memory reduces the update costs by allowing user-performed code changes instead of costly product returns or technician calls. The 4-Mbit boot block flash memory family provides full-function, blocked flash memories suitable for a wide range of applications. These applications include extended PC BIOS and ROM-able applications storage, digital cellular phone program and data storage, telecommunication boot/firmware, printer firmware/font storage and various other embedded applications where program and data storage are required. Reprogrammable systems, such as personal computers, are ideal applications for the 4-Mbit flash memory products. Increasing software sophistication greatens the probability that a code update will be required after the PC is shipped. For example, the emerging of "plug and play" standard in desktop and portable PCs enables autoconfiguration of ISA and PCI add-in cards. However, since the "plug and play" specification continues to evolve, a flash BIOS provides a costeffective capability to update existing PCs. In addition, the parameter blocks are ideal for storing the required auto-configuration parameters, allowing you to integrate the BIOS PROM and parameter storage EEPROM into a single component, reducing parts costs while increasing functionality.
1.4
Pinouts
Intel's SmartVoltage Boot Block architecture provides upgrade paths in every package pinout to the 8-Mbit density. The 28F004B 40-lead TSOP pinout for space-constrained designs is shown in Figure 3. The 28F400 44-lead PSOP pinout follows the industry-standard ROM/EPROM pinout, as shown in Figure 4. For designs that require x16 operation but have space concerns, refer to the 48-lead pinout in Figure 5. Furthermore, the 28F400 56-lead TSOP pinout shown in Figure 6 provides density upgrades to future higher density boot block memories. Pinouts for the corresponding 2-Mbit and 8-Mbit components are also provided for convenient reference. 4-Mbit pinouts are given on the chip illustration in the center, with 2-Mbit and 8-Mbit pinouts going outward from the center.
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4-MBIT SmartVoltage BOOT BLOCK FAMILY
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A[0:17]
A[18:1]
CS#
CE# OE#
WE#
RD#
WR#
i386TM EX CPU (25 MHz)
28F400BV-60
D[0:15]
RESET
DQ[0:15]
RP#
RESET
0530_01
NOTE: A data bus buffer may be needed for processor speeds above 25 MHz.
Figure 1. 28F400 Interface to Intel386TM EX Microprocessor
A[16:18]
ADDRESS LATCHES LE
A8-A15 80C188EB ALE AD0-AD7 ADDRESS LATCHES LE
A 0 -A 18
28F004-T
DQ 0 -DQ 7 UCS# VCC
10K
CE#
WR# RD# RESIN# System Reset P1.X P1.X VCC
WE# OE# RP# VPP
WP#
0530_02
Figure 2. 28F004B Interface to Intel80C188EB 8-Bit Embedded Microprocessor 8
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28F008B 28F002B
4-MBIT SmartVoltage BOOT BLOCK FAMILY
28F002B 28F008B
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
A 16 A 15 A 14 A 13 A 12 A 11 A9 A8 WE# RP# VPP WP# A 18 A7 A6 A5 A4 A3 A2 A1
A 16 A 15 A 14 A 13 A 12 A 11 A9 A8 WE# RP# VPP WP# NC A7 A6 A5 A4 A3 A2 A1
A 16 A 15 A 14 A 13 A 12 A 11 A9 A8 WE# RP# VPP WP# A 18 A7 A6 A5 A4 A3 A2 A1
28F004B Boot Block 40-Lead TSOP 10 mm x 20 mm TOP VIEW
A 17 GND NC NC A 10 DQ 7 DQ 6 DQ 5 DQ 4 VCC VCC NC DQ 3 DQ 2 DQ 1 DQ 0 OE# GND CE# A0
A 17 GND NC NC A 10 DQ 7 DQ 6 DQ 5 DQ 4 VCC VCC NC DQ 3 DQ 2 DQ 1 DQ 0 OE# GND CE# A0
A 17 GND NC A19 A 10 DQ 7 DQ 6 DQ 5 DQ 4 VCC VCC NC DQ 3 DQ 2 DQ 1 DQ 0 OE# GND CE# A0
0530_03
Figure 3. The 40-Lead TSOP Offers the Smallest Form Factor for Space-Constrained Applications
28F800 28F200
VPP A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 CE# GND OE# DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11 VPP WP# NC A7 A6 A5 A4 A3 A2 A1 A0 CE# GND OE# DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11 VPP WP# A17 A7 A6 A5 A4 A3 A2 A1 A0 CE# GND OE# DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 RP# WE# A8 A9 A 10 A 11 A 12 A 13 A 14 A 15 A 16 BYTE# GND DQ 15 /A -1 DQ 7 DQ 14 DQ 6 DQ 13 DQ 5 DQ 12 DQ 4 V CC
28F200
RP# WE# A8 A9 A 10 A 11 A 12 A 13 A 14 A 15 A 16 BYTE# GND DQ 15 /A -1 DQ 7 DQ 14 DQ 6 DQ 13 DQ 5 DQ 12 DQ 4 V CC
28F800
RP# WE# A8 A9 A 10 A 11 A 12 A 13 A 14 A 15 A 16 BYTE# GND DQ 15 /A -1 DQ 7 DQ 14 DQ 6 DQ 13 DQ 5 DQ 12 DQ 4 V CC
0530_04
PA28F400 Boot Block 44-Lead PSOP 0.525" x 1.110"
TOP VIEW
NOTE: Pin 2 is WP# on 2- and 4-Mbit devices but A18 on the 8-Mbit because no other pins were available for the high order address. Thus, the 8-Mbit in the 44-lead PSOP cannot unlock the boot block without RP# = VHH (12V). To allow upgrades to the 8 Mbit from 2/2 Mbit in this package, design pin 2 to control WP# at the 2/4 Mbit level and A at the 8-Mbit density. See 18 Section 3.4 for details.
Figure 4. The 44-Lead PSOP Offers a Convenient Upgrade from JEDEC ROM Standards
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28F800
A 15 A 14 A 13 A12 A11 A 10 A9 A8 NC NC W E# RP# V PP W P# NC A 18 A 17 A7 A6 A5 A4 A3 A2 A1
28F200
A 15 A 14 A 13 A12 A11 A 10 A9 A8 NC NC WE# RP# V PP WP# NC NC NC A7 A6 A5 A4 A3 A2 A1 A 15 A 14 A 13 A12 A11 A 10 A9 A8 NC NC WE# RP# V PP WP# NC NC A 17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A 16 BYTE# GND DQ15 /A -1 DQ 7 DQ 14 DQ 6 DQ 13 DQ 5 DQ 12 DQ 4 V CC DQ 11 DQ 3 DQ 10 DQ 2 DQ 9 DQ 1 DQ 8 DQ 0 OE# GND CE# A0
28F200
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28F800
A 16 BYTE# GND DQ15 /A -1 DQ 7 DQ 14 DQ 6 DQ 13 DQ 5 DQ 12 DQ 4 V CC DQ 11 DQ 3 DQ 10 DQ 2 DQ 9 DQ 1 DQ 8 DQ 0 OE# GND CE# A0
0530_05
28F400 Boot Block 48-Lead TSOP 12 mm x 20 mm TOP VIEW
A 16 BYTE# GND DQ15 /A -1 DQ 7 DQ 14 DQ 6 DQ 13 DQ 5 DQ 12 DQ 4 V CC DQ 11 DQ 3 DQ 10 DQ 2 DQ 9 DQ 1 DQ 8 DQ 0 OE# GND CE# A0
Figure 5. The 48-Lead TSOP Offers the Smallest Form Factor for x16 Operation
28F200
NC NC A 15 A 14 A 13 A 12 A 11 A 10 A9 A8 NC NC WE# RP# NC NC VPP WP# NC NC A7 A6 A5 A4 A3 A2 NC NC A 15 A 14 A 13 A 12 A 11 A 10 A9 A8 NC NC WE# RP# NC NC VPP WP# NC A 17 A7 A6 A5 A4 A3 A2 A1 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 NC A 16 BYTE# GND DQ 15 /A -1 DQ 7 DQ 14 DQ 6 DQ 13 DQ 5 DQ 12 DQ 4 VCC VCC DQ 11 DQ 3 DQ 10 DQ 2 DQ 9 DQ 1 DQ 8 DQ 0 OE# GND CE# A0 NC NC
28F200
NC A 16 BYTE#
GND DQ 15 /A -1 DQ 7 DQ 14 DQ 6 DQ 13 DQ 5 DQ 12 DQ 4 VCC VCC DQ 11 DQ 3 DQ 10 DQ 2 DQ 9 DQ 1 DQ 8 DQ 0 OE# GND CE# A0 NC NC
0530_06
28F400 56-Lead TSOP Boot Block 14 mm x 20 mm TOP VIEW
A1 NC
Figure 6. The 56-Lead TSOP Offers Compatibility between 2 and 4 Mbits
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1.5
Symbol A0-A18 A9 DQ0-DQ7 DQ8-DQ15
4-MBIT SmartVoltage BOOT BLOCK FAMILY
Pin Descriptions
Table 2. 28F400/004 Pin Descriptions Type INPUT Name and Function ADDRESS INPUTS for memory addresses. Addresses are internally latched during a write cycle. The 28F400 only has A0- A17 pins, while the 28F004B has A0- A18. ADDRESS INPUT: When A9 is at V HH the signature mode is accessed. During this mode, A0 decodes between the manufacturer and device IDs. When BYTE# is at a logic low, only the lower byte of the signatures are read. DQ 15/A-1 is a don't care in the signature mode when BYTE# is low.
INPUT
INPUT/ DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle OUTPUT during a Program command. Inputs commands to the Command User Interface when CE# and WE# are active. Data is internally latched during the write cycle. Outputs array, Intelligent Identifier and Status Register data. The data pins float to tri-state when the chip is de-selected or the outputs are disabled. INPUT/ DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle OUTPUT during a Program command. Data is internally latched during the write cycle. Outputs array data. The data pins float to tri-state when the chip is de-selected or the outputs are disabled as in the byte-wide mode (BYTE# = "0"). In the byte-wide mode DQ15/A-1 becomes the lowest order address for data output on DQ0-DQ7. The 28F004B does not include these DQ8-DQ15 pins. INPUT CHIP ENABLE: Activates the device's control logic, input buffers, decoders and sense amplifiers. CE# is active low. CE# high de-selects the memory device and reduces power consumption to standby levels. If CE# and RP# are high, but not at a CMOS high level, the standby current will increase due to current flow through the CE# and RP# input stages. OUTPUT ENABLE: Enables the device's outputs through the data buffers during a read cycle. OE# is active low. WRITE ENABLE: Controls writes to the Command Register and array blocks. WE# is active low. Addresses and data are latched on the rising edge of the WE# pulse. RESET/DEEP POWER-DOWN: Uses three voltage levels (V IL, VIH, and VHH) to control two different functions: reset/deep power-down mode and boot block unlocking. It is backwards-compatible with the BX/BL/BV products. When RP# is at logic low, the device is in reset/deep power-down mode, which puts the outputs at High-Z, resets the Write State Machine, and draws minimum current. When RP# is at logic high, the device is in standard operation. When RP# transitions from logic-low to logic-high, the device defaults to the read array mode. When RP# is at VHH, the boot block is unlocked and can be programmed or erased. This overrides any control from the WP# input.
CE#
OE# WE#
INPUT INPUT
RP#
INPUT
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Table 2. 28F400/004 Pin Descriptions (Continued) Symbol WP# Type INPUT Name and Function
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WRITE PROTECT: Provides a method for unlocking the boot block in a system without a 12V supply. When WP# is at logic low, the boot block is locked, preventing program and erase operations to the boot block. If a program or erase operation is attempted on the boot block when WP# is low, the corresponding status bit (bit 4 for program, bit 5 for erase) will be set in the Status Register to indicate the operation failed. When WP# is at logic high, the boot block is unlocked and can be programmed or erased. NOTE: This feature is overridden and the boot block unlocked when RP# is at VHH. See Section 3.4 for details on write protection.
BYTE#
INPUT
BYTE# ENABLE: Not available on 28F004B. Controls whether the device operates in the byte-wide mode (x8) or the word-wide mode (x16). BYTE# pin must be controlled at CMOS levels to meet the CMOS current specification in the standby mode. When BYTE# is at logic low, the byte-wide mode is enabled, where data is read and programmed on DQ0-DQ7 and DQ15/A-1 becomes the lowest order address that decodes between the upper and lower byte. DQ8-DQ14 are tri-stated during the byte-wide mode. When BYTE# is at logic high, the word-wide mode is enabled, where data is read and programmed on DQ0-DQ15.
VCC VPP
DEVICE POWER SUPPLY: 5.0V 10%, 3.3 0.3V, 2.7V-3.6V (BE/CE only) PROGRAM/ERASE POWER SUPPLY: For erasing memory array blocks or programming data in each block, a voltage either of 5V 10% or 12V 5% must be applied to this pin. When VPP < VPPLK all blocks are locked and protected against Program and Erase commands. GROUND: For all internal circuitry. NO CONNECT: Pin may be driven or left floating.
GND NC
12
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2.0 2.1
2.1.1
4-MBIT SmartVoltage BOOT BLOCK FAMILY
2.1.2 TWO 8-KB PARAMETER BLOCKS
PRODUCT DESCRIPTION Memory Blocking Organization
This product family features an asymmetricallyblocked architecture providing system memory integration. Each erase block can be erased independently of the others up to 100,000 times for commercial temperature or up to 10,000 times for extended temperature. The block sizes have been chosen to optimize their functionality for common applications of nonvolatile storage. The combination of block sizes in the boot block architecture allow the integration of several memories into a single chip. For the address locations of the blocks, see the memory maps in Figures 4 and 5. ONE 16-KB BOOT BLOCK
The boot block architecture includes parameter blocks to facilitate storage of frequently updated small parameters that would normally require an EEPROM. By using software techniques, the byterewrite functionality of EEPROMs can be emulated. These techniques are detailed in Intel's application note, AP-604 Using Intel's Boot Block Flash Memory Parameter Blocks to Replace EEPROM. Each boot block component contains two parameter blocks of 8 Kbytes (8,192 bytes) each. The parameter blocks are not write-protectable. 2.1.3 ONE 96-KB + THREE 128-KB MAIN BLOCKS
The boot block is intended to replace a dedicated boot PROM in a microprocessor or microcontrollerbased system. The 16-Kbyte (16,384 bytes) boot block is located at either the top (denoted by -T suffix) or the bottom (-B suffix) of the address map to accommodate different microprocessor protocols for boot code location. This boot block features hardware controllable write-protection to protect the crucial microprocessor boot code from accidental modification. The protection of the boot block is controlled using a combination of the VPP, RP#, and WP# pins, as is detailed in Section 3.4.
After the allocation of address space to the boot and parameter blocks, the remainder is divided into main blocks for data or code storage. Each 4-Mbit device contains one 96-Kbyte (98,304 byte) block and three 128-Kbyte (131,072 byte) blocks. See the memory maps for each device for more information.
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28F400-B
3FFFFH 128-Kbyte MAIN BLOCK 30000H 2FFFFH 20000H 1FFFFH 10000H 0FFFFH 04000H 03FFFH 03000H 02FFFH 02000H 01FFFH 00000H
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28F400-T
3FFFFH 3E000H 3DFFFH 3D000H 3CFFFH 3C000H 3BFFFH 30000H 2FFFFH 128-Kbyte MAIN BLOCK 20000H 1FFFFH 128-Kbyte MAIN BLOCK 10000H 0FFFFH 128-Kbyte MAIN BLOCK 00000H 16-Kbyte BOOT BLOCK 8-Kbyte PARAMETER BLOCK 8-Kbyte PARAMETER BLOCK 96-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
96-Kbyte MAIN BLOCK 8-Kbyte PARAMETER BLOCK 8-Kbyte PARAMETER BLOCK 16-Kbyte BOOT BLOCK
NOTE: Address = A[17:0]. In x8 operation, the least significant system address should be connected to A . Memory maps are -1 shown for x16 operation.
Figure 7. Word-Wide x16-Mode Memory Maps
28F004-T
7FFFFH 7FFFFH
28F004-B
16-Kbyte BOOT BLOCK
7C000H 7BFFFH 7A000H 79FFFH 78000H 77FFFH 60000H 5FFFFH
128-Kbyte MAIN BLOCK
60000H 5FFFFH
8-Kbyte PARAMETER BLOCK 8-Kbyte PARAMETER BLOCK 96-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
40000H 3FFFFH
128-Kbyte MAIN BLOCK 128-Kbyte MAIN BLOCK
20000H 1FFFFH
40000H 3FFFFH
96-Kbyte MAIN BLOCK 128-Kbyte MAIN BLOCK
08000H 07FFFH 06000H 05FFFH 04000H 03FFFH 00000H
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8-Kbyte PARAMETER BLOCK 8-Kbyte PARAMETER BLOCK 16-Kbyte BOOT BLOCK
20000H 1FFFFH
128-Kbyte MAIN BLOCK
00000H
NOTE: Address = A[18:0]. These memory maps apply to the 28F004B or the 28F400 in x8 mode.
Figure 8. Byte-Wide x8-Mode Memory Maps
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3.0
4-MBIT SmartVoltage BOOT BLOCK FAMILY
PRODUCT FAMILY PRINCIPLES OF OPERATION
3.2
3.2.1
Read Operations
READ ARRAY
Flash memory combines EPROM functionality with in-circuit electrical write and erase. The boot block flash family utilizes a Command User Interface (CUI) and automated algorithms to simplify write and erase operations. The CUI allows for 100% TTL-level control inputs, fixed power supplies during erasure and programming, and maximum EPROM compatibility. When VPP < VPPLK, the device will only successfully execute the following commands: Read Array, Read Status Register, Clear Status Register and intelligent identifier mode. The device provides standard EPROM read, standby and output disable operations. Manufacturer identification and device identification data can be accessed through the CUI or through the standard EPROM A9 high voltage access (VID) for PROM programming equipment. The same EPROM read, standby and output disable functions are available when 5V or 12V is applied to the VPP pin. In addition, 5V or 12V on VPP allows write and erase of the device. All functions associated with altering memory contents: Program and Erase, Intelligent Identifier Read, and Read Status are accessed via the CUI. The internal Write State Machine (WSM) completely automates program and erase, beginning operation signaled by the CUI and reporting status through the Status Register. The CUI handles the WE# interface to the data and address latches, as well as system status requests during WSM operation.
When RP# transitions from VIL (reset) to VIH, the device will be in the read array mode and will respond to the read control inputs (CE#, address inputs, and OE#) without any commands being written to the CUI. When the device is in the read array mode, five control signals must be controlled to obtain data at the outputs. * * * * * RP# must be logic high (VIH) WE# must be logic high (VIH) BYTE# must be logic high or logic low CE# must be logic low (VIL) OE must be logic low (V IL)
In addition, the address of the desired location must be applied to the address pins. Refer to Figures 15 and 16 for the exact sequence and timing of these signals. If the device is not in read array mode, as would be the case after a program or erase operation, the Read Mode command (FFH) must be written to the CUI before reads can take place. During system design, consideration should be taken to ensure address and control inputs meet required input slew rates of <10 ns as defined in Figures 12 and 13.
3.1
Bus Operations
Flash memory reads, erases and writes in-system via the local CPU. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. These bus operations are summarized in Tables 3 and 4.
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Table 3. Bus Operations for Word-Wide Mode (BYTE# = VIH) Mode Read Output Disable Standby Deep Power-Down Intelligent Identifier (Mfr) Intelligent Identifier (Device) Write 9 4 4,5 6,7,8 Notes 1,2,3 RP# VIH VIH VIH VIL VIH VIH VIH CE# VIL VIL VIH X VIL VIL VIL OE# VIL VIH X X VIL VIL VIH WE# VIH VIH X X VIH VIH VIL A9 X X X X VID VID X A0 X X X X VIL VIH X VPP X X X X X X X
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DQ0-15 DOUT High Z High Z High Z 0089 H See Table 5 DIN
Table 4. Bus Operations for Byte-Wide Mode (BYTE# = VIL) Mode Read Output Disable Standby Deep PowerDown Intelligent Identifier (Mfr) Intelligent Identifier (Device) Write 9 4 4,5 Notes 1,2,3 RP# VIH VIH VIH VIL VIH VIH CE# VIL VIL VIH X VIL VIL OE# VIL VIH X X VIL VIL WE# VIH VIH X X VIH VIH A9 X X X X VID VID A0 X X X X VIL VIH A-1 X X X X X X VPP X X X X X X DQ0-7 DOUT High Z High Z High Z 89H See Table 5 DIN DQ8-14 High Z High Z High Z High Z High Z High Z
6,7,8
VIH
VIL
VIH
VIL
X
X
X
X
High Z
NOTES: 1. Refer to DC Characteristics. 2. X can be VIL, VIH for control pins and addresses, VPPLK or VPPH for VPP. 3. See DC Characteristics for VPPLK, VPPH1, VPPH2, VHH, VID voltages. 4. Manufacturer and device codes may also be accessed via a CUI write sequence, A1-A17 = X, A1-A18 = X. 5. See Table 5 for device IDs. 6. Refer to Table 7 for valid DIN during a write operation. 7. Command writes for block erase or word/byte program are only executed when V = VPPH1 or VPPH2. PP 8. To write or erase the boot block, hold RP# at VHH or WP# at VIH. See Section 3.4. 9. RP# must be at GND 0.2V to meet the maximum deep power-down current specified.
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3.2.2 INTELLIGENT IDENTIFIERS To read the manufacturer and device codes, the device must be in intelligent identifier read mode, which can be reached using two methods: by writing the intelligent identifier command (90H) or by taking the A9 pin to VID. Once in intelligent identifier read mode, A0 = 0 outputs the manufacturer's identification code and A0 = 1 outputs the device code. In byte-wide mode, only the lower byte of the above signatures is read (DQ15/A-1 is a "don't care" in this mode). See Table 5 for product signatures. To return to read array mode, write a Read Array command (FFH). Table 5. Intelligent Identifier Table Product Mfr. ID Device ID -T -B (Top Boot) (Bottom Boot) 28F400 28F004 0089 H 89 H 4470 H 78 H 4471 H 79 H
4-MBIT SmartVoltage BOOT BLOCK FAMILY
3.3
3.3.1
Write Operations
COMMAND USER INTERFACE (CUI)
The Command User Interface (CUI) is the interface between the microprocessor and the internal chip controller. Commands are written to the CUI using standard microprocessor write timings. The available commands are Read Array, Read Intelligent Identifier, Read Status Register, Clear Status Register, Erase and Program (summarized in Tables 6 and 7). The three read modes are read array, intelligent identifier read, and status register read. For Program or Erase commands, the CUI informs the Write State Machine (WSM) that a write or erase has been requested. During the execution of a Program command, the WSM will control the programming sequences and the CUI will only respond to status reads. During an erase cycle, the CUI will respond to status reads and erase suspend. After the WSM has completed its task, it will set the WSM Status bit to a "1" (ready), which indicates that the CUI can respond to its full command set. Note that after the WSM has returned control to the CUI, the CUI will stay in the current command state until it receives another command. 3.3.1.1 Command Function Description
Device operations are selected by writing specific commands into the CUI. Tables 6 and 7 define the available commands.
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Decription
Table 6. Command Codes and Descriptions Code Device Mode 00 FF 40 Invalid/ Reserved Read Array Program Set-Up
Unassigned commands that should not be used. Intel reserves the right to redefine these codes for future functions. Places the device in read array mode, so that array data will be output on the data pins. Sets the CUI into a state such that the next write will latch the Address and Data registers on the rising edge and begin the program algorithm. The device then defaults to the read status mode, where the device outputs Status Register data when OE# is enabled. To read the array, issue a Read Array command. To cancel a program operation after issuing a Program Set-Up command, write all 1's (FFH for x8, FFFFH for x16) to the CUI. This will return to read status register mode after a standard program time without modifying array contents. If a program operation has already been initiated to the WSM this command can not cancel that operation in progress.
10 20
Alternate Prog Set-Up Erase Set-Up
(See 40H/Program Set-Up) Prepares the CUI for the Erase Confirm command. If the next command is not an Erase Confirm command, then the CUI will set both the Program Status (SR.4) and Erase Status (SR.5) bits of the Status Register to a "1," place the device into the read Status Register state, and wait for another command without modifying array contents. This can be used to cancel an erase operation after the Erase Setup command has been issued. If an operation has already been initiated to the WSM this can not cancel that operation in progress. If the previous command was an Erase Set-Up command, then the CUI will latch address and data, and begin erasing the block indicated on the address pins. During erase, the device will respond only to the Read Status Register and Erase Suspend commands and will output Status Register data when OE# is toggled low. Status Register data is updated by toggling either OE# or CE# low. Valid only while an erase operation is in progress and will be ignored in any other circumstance. Issuing this command will begin to suspend erase operation. The Status Register will indicate when the device reaches erase suspend mode. In this mode, the CUI will respond only to the Read Array, Read Status Register, and Erase Resume commands and the WSM will also set the WSM Status bit to a "1" (ready). The WSM will continue to idle in the SUSPEND state, regardless of the state of all input control pins except RP#, which will immediately shut down the WSM and the remainder of the chip, if it is made active. During a suspend operation, the data and address latches will remain closed, but the address pads are able to drive the address into the read path. See Section 3.3.4.1. Puts the device into the read Status Register mode, so that reading the device outputs Status Register data, regardless of the address presented to the device. The device automatically enters this mode after program or erase has completed. This is one of the two commands that is executable while the WSM is operating. See Section 3.3.2.
D0
Erase Resume/ Erase Confirm Erase Suspend
B0
70
Read Status Register
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Code Device Mode 50 Clear Status Register 90 Intelligent Identifier
4-MBIT SmartVoltage BOOT BLOCK FAMILY
Table 6. Command Codes and Descriptions (Continued) Decription The WSM can only set the Program Status and Erase Status bits in the Status Register to "1;" it cannot clear them to "0." The Status Register operates in this fashion for two reasons. The first is to give the host CPU the flexibility to read the status bits at any time. Second, when programming a string of bytes, a single Status Register query after programming the string may be more efficient, since it will return the accumulated error status of the entire string. See Section 3.3.2.1. Puts the device into the intelligent identifier read mode, so that reading the device will output the manufacturer and device codes. (A0 = 0 for manufacturer, A0 = 1 for device, all other address inputs are ignored). See Section 3.2.2. Table 7. Command Bus Definitions First Bus Cycle Second Bus Cycle Oper Addr Data
Command Read Array Intelligent Identifier Read Status Register Clear Status Register Word/Byte Program Alternate Word/Byte Program Block Erase/Confirm Erase Suspend Erase Resume
ADDRESS BA = Block Address IA = Identifier Address PA = Program Address X = Don't Care
Note 8 1 2,4 3
Oper Write Write Write Write Write
Addr X X X X PA PA BA X X
Data FFH 90H 70H 50H 40H 10H 20H B0H D0H
Read Read
IA X
IID SRD
Write Write Write
PA PA BA
PD PD D0H
6,7 6,7 5
Write Write Write Write
DATA SRD = Status Register Data IID = Identifier Data PD = Program Data
NOTES:
1. 2. 3. 4. 5. 6. 7. 8. Bus operations are defined in Tables 3 and 4. IA = Identifier Address: A0 = 0 for manufacturer code, A0 = 1 for device code. SRD - Data read from Status Register. IID = Intelligent Identifier Data. Following the Intelligent Identifier command, two read operations access manufacturer and device codes. BA = Address within the block being erased. PA = Address to be programmed. PD = Data to be programmed at location PA. Either 40H or 10H commands is valid. When writing commands to the device, the upper data bus [DQ8-DQ15] = X (28F400 only) which is either VIL or VIH, to minimize current draw.
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Table 8. Status Register Bit Definition WSMS 7 ESS 6 ES 5 DWS 4 VPPS 3 R 2 NOTES: SR.7 =WRITE STATE MACHINE STATUS 1 = Ready (WSMS) 0 = Busy SR.6 = ERASE-SUSPEND STATUS (ESS) 1 = Erase Suspended 0 = Erase In Progress/Completed SR.5 = ERASE STATUS (ES) 1 = Error In Block Erasure 0 = Successful Block Erase SR.4 = PROGRAM STATUS (DWS) 1 = Error in Byte/Word Program 0 = Successful Byte/Word Program SR.3 = VPP STATUS (VPPS) 1 = VPP Low Detect, Operation Abort 0 = VPP OK R 1
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R 0
Check Write State Machine bit first to determine Word/Byte program or Block Erase completion, before checking Program or Erase Status bits. When Erase Suspend is issued, WSM halts execution and sets both WSMS and ESS bits to "1." ESS bit remains set to "1" until an Erase Resume command is issued. When this bit is set to "1," WSM has applied the max number of erase pulses to the block and is still unable to verify successful block erasure. When this bit is set to "1," WSM has attempted but failed to program a byte or word. The VPP Status bit does not provide continuous indication of VPP level. The WSM interrogates VPP level only after the Byte Write or Erase command sequences have been entered, and informs the system if V PP has not been switched on. The VPP Status bit is not guaranteed to report accurate feedback between VPPLK and VPPH. These bits are reserved for future use and should be masked out when polling the Status Register.
SR.2-SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R)
3.3.2
STATUS REGISTER
The device Status Register indicates when a program or erase operation is complete, and the success or failure of that operation. To read the Status Register write the Read Status (70H) command to the CUI. This causes all subsequent read operations to output data from the Status Register until another command is written to the CUI. To return to reading from the array, issue a Read Array (FFH) command. The Status Register bits are output on DQ0-DQ7, in both byte-wide (x8) or word-wide (x16) mode. In the word-wide mode the upper byte, DQ8-DQ15, outputs 00H during a Read Status command. In the byte-wide mode, DQ8-DQ14 are tri-stated and DQ15/A-1 retains the low order address function. 20
Important: The contents of the Status Register are latched on the falling edge of OE# or CE#, whichever occurs last in the read cycle. This prevents possible bus errors which might occur if Status Register contents change while being read. CE# or OE# must be toggled with each subsequent status read, or the Status Register will not indicate completion of a program or erase operation. When the WSM is active, the SR.7 register will indicate the status of the WSM, and will also hold the bits indicating whether or not the WSM was successful in performing the desired operation.
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3.3.2.1 3.3.3
4-MBIT SmartVoltage BOOT BLOCK FAMILY
The Status Register should be cleared before attempting the next operation. Any CUI instruction can follow after programming is completed; however, reads from the Memory Array or Intelligent Identifier cannot be accomplished until the CUI is given the appropriate command. 3.3.4 ERASE MODE
Clearing the Status Register
The WSM sets status bits 3 through 7 to "1," and clears bits 6 and 7 to "0," but cannot clear status bits 3 through 5 to "0." Bits 3 through 5 can only be cleared by the controlling CPU through the use of the Clear Status Register (50H) command, because these bits indicate various error conditions. By allowing the system software to control the resetting of these bits, several operations may be performed (such as cumulatively programming several bytes or erasing multiple blocks in sequence) before reading the Status Register to determine if an error occurred during that series. Clear the Status Register before beginning another command or sequence. Note, again, that a Read Array command must be issued before data can be read from the memory or intelligent identifier. PROGRAM MODE
To erase a block, write the Erase Set-Up and Erase Confirm commands to the CUI, along with the addresses identifying the block to be erased. These addresses are latched internally when the Erase Confirm command is issued. Block erasure results in all bits within the block being set to "1." Only one block can be erased at a time. The WSM will execute a sequence of internally timed events to: 1. Program all bits within the block to "0." 2. Verify that all bits within the block are sufficiently programmed to "0." 3. Erase all bits within the block to "1." 4. Verify that all bits within the block are sufficiently erased. While the erase sequence is executing, bit 7 of the Status Register is a "0." When the Status Register indicates that erasure is complete, check the Erase Status bit to verify that the erase operation was successful. If the Erase operation was unsuccessful, bit 5 of the Status Register will be set to a "1," indicating an Erase Failure. If VPP was not within acceptable limits after the Erase Confirm command is issued, the WSM will not execute an erase sequence; instead, bit 5 of the Status Register is set to a "1" to indicate an Erase Failure, and bit 3 is set to a "1" to identify that VPP supply voltage was not within acceptable limits. Clear the Status Register before attempting the next operation. Any CUI instruction can follow after erasure is completed; however, reads from the Memory Array, Status Register, or Intelligent Identifier cannot be accomplished until the CUI is given the Read Array command.
Programming is executed using a two-write sequence. The Program Setup command is written to the CUI followed by a second write which specifies the address and data to be programmed. The WSM will execute a sequence of internally timed events to: 1. Program the desired bits of the addressed memory word or byte. 2. Verify that the desired bits are sufficiently programmed. Programming of the memory results in specific bits within a byte or word being changed to a "0." If the user attempts to program "1"s, there will be no change of the memory cell content and no error occurs. The Status Register indicates programming status: while the program sequence is executing, bit 7 of the Status Register is a "0." The Status Register can be polled by toggling either CE# or OE#. While programming, the only valid command is Read Status Register. When programming is complete, the Program Status bits should be checked. If the programming operation was unsuccessful, bit 4 of the Status Register is set to a "1" to indicate a Program Failure. If bit 3 is set to a "1," then VPP was not within acceptable limits, and the WSM did not execute the programming sequence.
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3.3.4.1 Suspending and Resuming Erase 3.4.2
WP# = VIL FOR BOOT BLOCK LOCKING
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Since an erase operation requires on the order of seconds to complete, an Erase Suspend command is provided to allow erase-sequence interruption in order to read data from another block of the memory. Once the erase sequence is started, writing the Erase Suspend command to the CUI requests that the WSM pause the erase sequence at a predetermined point in the erase algorithm. The Status Register will indicate if/when the erase operation has been suspended. At this point, a Read Array command can be written to the CUI in order to read data from blocks other than that which is being suspended. The only other valid command at this time is the Erase Resume command or Read Status Register command. During erase suspend mode, the chip can go into a pseudo-standby mode by taking CE# to VIH, which reduces active current draw. To resume the erase operation, enable the chip by taking CE# to VIL, then issuing the Erase Resume command, which continues the erase sequence to completion. As with the end of a standard erase operation, the Status Register must be read, cleared, and the next instruction issued in order to continue.
When WP# = VIL, the boot block is locked and any program or erase operation to the boot block will result in an error in the Status Register. All other blocks remain unlocked in this condition and can be programmed or erased normally. Note that this feature is overridden and the boot block unlocked when RP# = VHH. 3.4.3 RP# = VHH OR WP# = VIH FOR BOOT BLOCK UNLOCKING
Two methods can be used to unlock the boot block: 1. WP# = VIH 2. RP# = VHH If both or either of these two conditions are met, the boot block will be unlocked and can be programmed or erased. 3.4.4 UPGRADE NOTE FOR 8-MBIT 44-PSOP PACKAGE
3.4
Boot Block Locking
The boot block family architecture features a hardware-lockable boot block so that the kernel code for the system can be kept secure while the parameter and main blocks are programmed and erased independently as necessary. Only the boot block can be locked independently from the other blocks. The truth table, Table 9, clearly defines the write protection methods. 3.4.1 VPP = VIL FOR COMPLETE PROTECTION
If upgradability to 8M is required, note that the 8-Mbit in the 44-PSOP does not have a WP# because no pins were available for the 8-Mbit upgrade address. Thus, in this density-package combination only, VHH (12V) on RP# is required to unlock the boot block. Unlocking with a logic-level signal is not possible. If this functionality is required, and 12V is not available, consider using the 48-TSOP package, which has a WP# pin and can be unlocked with a logic-level signal. All other density-package combinations have WP# pins. Table 9. Write Protection Truth Table VPP VIL VPPLK VPPLK VPPLK VPPLK RP# X VIL VHH VIH VIH WP# X X X VIL VIH Write Protection Provided All Blocks Locked All Blocks Locked (Reset) All Blocks Unlocked Boot Block Locked All Blocks Unlocked
For complete write protection of all blocks in the flash device, the VPP programming voltage can be held low. When VPP is below VPPLK, any program or erase operation will result in a error in the Status Register.
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Start Write 40H, Word/Byte Address Write Word/Byte Data/Address Read Status Register NO SR.7 = 1 ? YES Full Status Check if Desired
4-MBIT SmartVoltage BOOT BLOCK FAMILY
Bus Operation Write
Command
Comments
Setup Program Program
Data = 40H Addr = Word/Byte to Program Data = Data to Program Addr = Location to Program
Write
Read
Status Register Data Toggle CE# or OE# to Update SRD. Check SR.7 1 = WSM Ready 0 = WSM Busy
Standby
Repeat for subsequent word/byte program operations. SR Full Status Check can be done after each word/byte program, or after a sequence of word/byte programs. Write FFH after the last program operation to reset device to read array mode.
Word/Byte Program Complete
FULL STATUS CHECK PROCEDURE
Read Status Register Data (See Above)
Bus Operation
Command
Comments
Standby SR.3= 0 1 SR.4 = 0 Word/Byte Program Successful Word/Byte Program Error 1 VPP Range Error
Check SR.3 1 = VPP Low Detect
Standby
Check SR.4 1 = Word/Byte Program Error
SR.3 MUST be cleared, if set during a program attempt, before further attempts are allowed by the Write State Machine. SR.4 is only cleared by the Clear Status Register command, in cases where multiple bytes are programmed before full status is checked. If error is detected, clear the Status Register before attempting retry or other error recovery.
0530_09
Figure 9. Automated Word/Byte Programming Flowchart
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Command Comments Write Erase Setup Data = 20H Addr = Within Block to Be Erased Data = D0H Addr = Within Block to Be Erased Status Register Data Toggle CE# or OE# to Update Status Register Check SR.7 1 = WSM Ready 0 = WSM Busy Write Erase Confirm
Start
Bus Operation
Write 20H, Block Address
Write D0H and Block Address
Read Read Status Register NO 0 SR.7 =
Suspend Erase Loop YES
Standby
Suspend Erase
1 Full Status Check if Desired
Repeat for subsequent block erasures. Full Status Check can be done after each block erase, or after a sequence of block erasures. Write FFH after the last operation to reset device to read array mode.
Block Erase Complete
FULL STATUS CHECK PROCEDURE
Read Status Register Data (See Above)
Bus Operation Standby
Command
Comments Check SR.3 1 = VPP Low Detect
SR.3 = 0
1
VPP Range Error Standby Check SR.4,5 Both 1 = Command Sequence Error Check SR.5 1 = Block Erase Error
1 SR.4,5 = 0 1 SR.5 = 0
Command Sequence Error
Standby
SR.3 MUST be cleared, if set during an erase attempt, before further attempts are allowed by the Write State Machine. Block Erase Error SR.5 is only cleared by the Clear Status Register Command, in cases where multiple blocks are erase before full status is checked. If error is detected, clear the Status Register before attempting retry or other error recovery.
Block Erase Successful
0530_10
Figure 10. Automated Block Erase Flowchart 24
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Start Write B0H Read Status Register 0 SR.7 = 1 0 CSR.6 = 1 Write FFH
4-MBIT SmartVoltage BOOT BLOCK FAMILY
Bus Operation Write
Command Erase Suspend
Comments Data = B0H Addr = X Status Register Data Toggle CE# or OE# to Update SRD Addr = X Check SR.7 1 = WSM Ready 0 = WSM Busy Check SR.6 1 = Erase Suspended 0 = Erase Completed
Read
Standby
Standby
Write Erase Completed Read
Read Array
Data = FFH Addr = X Read array data from block other than the one being erased. Data = D0H Addr = X
Write
Erase Resume
Read Array Data
Done Reading YES
NO
Write D0H
Write FFH
Erase Resumed
Read Array Data
0530_11
Figure 11. Erase Suspend/Resume Flowchart
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3.5
3.5.1
Power Consumption
ACTIVE POWER
With CE# at a logic-low level and RP# at a logichigh level, the device is placed in the active mode. Refer to the DC Characteristics table for ICC current values. 3.5.2 AUTOMATIC POWER SAVINGS (APS)
During erase or program modes, RP# low will abort either erase or program operations, but the memory contents are no longer valid as the data has been corrupted by the RP# function. As in the read mode above, all internal circuitry is turned off to achieve the power savings. RP# transitions to VIL, or turning power off to the device will clear the Status Register.
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3.6
Power-Up/Down Operation
Automatic Power Savings (APS) provides lowpower operation during active mode. Power Reduction Control (PRC) circuitry allows the device to put itself into a low current state when not being accessed. After data is read from the memory array, PRC logic controls the device's power consumption by entering the APS mode where typical ICC current is less than 1 mA. The device stays in this static state with outputs valid until a new location is read. 3.5.3 STANDBY POWER
The device is protected against accidental block erasure or programming during power transitions. Power supply sequencing is not required, since the device is indifferent as to which power supply, VPP or VCC, powers-up first. The CUI is reset to the read mode after power-up, but the system must drop CE# low or present a new address to ensure valid data at the outputs. A system designer must guard against spurious writes when VCC voltages are above VLKO and VPP is active. Since both WE# and CE# must be low for a command write, driving either signal to VIH will inhibit writes to the device. The CUI architecture provides additional protection since alteration of memory contents can only occur after successful completion of the two-step command sequences. The device is also disabled until RP# is brought to VIH, regardless of the state of its control inputs. By holding the device in reset (RP# connected to system PowerGood) during power-up/down, invalid bus conditions during power-up can be masked, providing yet another level of memory protection. 3.6.1 RP# CONNECTED TO SYSTEM RESET
With CE# at a logic-high level (VIH), and the CUI in read mode, the memory is placed in standby mode, which disables much of the device's circuitry and substantially reduces power consumption. Outputs (DQ0-DQ15 or DQ0-DQ7) are placed in a highimpedance state independent of the status of the OE# signal. When CE# is at logic-high level during erase or program operations, the device will continue to perform the operation and consume corresponding active power until the operation is completed. 3.5.4 DEEP POWER-DOWN MODE
The SmartVoltage boot block family supports a low typical ICC in deep power-down mode, which turns off all circuits to save power. This mode is activated by the RP# pin when it is at a logic-low (GND 0.2V). Note: BYTE# pin must be at CMOS levels to meet the I CCD specification. During read modes, the RP# pin going low deselects the memory and places the output drivers in a high impedance state. Recovery from the deep power-down state, requires a minimum access time of tPHQV (see AC Characteristics table).
The use of RP# during system reset is important with automated write/erase devices because the system expects to read from the flash memory when it comes out of reset. If a CPU reset occurs without a flash memory reset, proper CPU initialization would not occur because the flash memory may be providing status information instead of array data. Intel's Flash memories allow proper CPU initialization following a system reset by connecting the RP# pin to the same RESET# signal that resets the system CPU.
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3.6.2
4-MBIT SmartVoltage BOOT BLOCK FAMILY
Transient current magnitudes depend on the device outputs' capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress these transient voltage peaks. Each flash device should have a 0.1 F ceramic capacitor connected between each VCC and GND, and between its VPP and GND. These highfrequency, inherently low-inductance capacitors should be placed as close as possible to the package leads. 3.7.1 VPP TRACE ON PRINTED CIRCUIT BOARDS
VCC, VPP AND RP# TRANSITIONS
The CUI latches commands as issued by system software and is not altered by VPP or CE# transitions or WSM actions. Its default state upon power-up, after exit from deep power-down mode, or after VCC transitions above VLKO (Lockout voltage), is read array mode. After any word/byte write or block erase operation is complete and even after VPP transitions down to VPPLK, the CUI must be reset to read array mode via the Read Array command if accesses to the flash memory are desired. Please refer to Intel's application note AP-617 Additional Flash Data Protection Using VPP, RP#, and WP#, for a circuit-level discription of how to implement the protection discussed in Section 3.6.
3.7
Power Supply Decoupling
Flash memory's power switching characteristics require careful device decoupling methods. System designers should consider three supply current issues: 1. Standby current levels (ICCS) 2. Active current levels (I CCR) 3. Transient peaks produced by falling and rising edges of CE#.
Designing for in-system writes to the flash memory requires special consideration of the VPP power supply trace by the printed circuit board designer. The VPP pin supplies the flash memory cells current for programming and erasing. One should use similar trace widths and layout considerations given to the VCC power supply trace. Adequate VPP supply traces, and decoupling capacitors placed adjacent to the component, will decrease spikes and overshoots.
NOTE: Table headings in Sections 5 and 6 (i.e., BV-60, BV-80, BV-120, TBV-80, TBE-120) refer to the specific products listed below. See Appendix A for more information on product naming and line items. Abbreviation BV-60 BV-80 BV-120 TBV-80 TBE-120 Applicable Product Names E28F004BV-T60, E28F004BV-B60, PA28F400BV-T60, PA28F400BV-B60, E28F400CV-T60, E28F400CV-B60, E28F400BV-T60, E28F400BV-B60 E28F004BV-T80, E28F004BV-B80, PA28F400BV-T80, PA28F400BV-B80, E28F400CV-T80, E28F400CV-B80, E28F400BV-T80, E28F400BV-B80 E28F004BV-T120, E28F004BV-B120, PA28F400BV-T120, PA28F400BV-B120 TE28F004BV-T80, TE28F004BV-B80, TB28F400BV-T80, TB28F400BV-B80, TE28F400CV-T80, TE28F400CV-B80, TE28F400BV-T80, TE28F400BV-B80 TE28F004BE-T120, TE28F004BE-B120, TE28F400CE-T120, TE28F400CE-B120
PRELIMINARY
27
4-MBIT SmartVoltage BOOT BLOCK FAMILY
4.0
ABSOLUTE MAXIMUM RATINGS*
Commercial Operating Temperature During Read .................................0C to +70C During Block Erase and Word/Byte Program ...............0C to +70C Temperature Bias.....................-10C to +80C Extended Operating Temperature During Read .............................-40C to +85C During Block Erase and Word/Byte Program ...........-40C to +85C Temperature Under Bias ..........-40C to +85C Storage Temperature....................-65C to +125C Voltage on Any Pin (except VCC, VPP, A9 and RP#) with Respect to GND..............-2.0V to +7.0V(2) Voltage on Pin RP# or Pin A9 with Respect to GND......... -2.0V to +13.5V(2,3) VPP Program Voltage with Respect to GND during Block Erase and Word/Byte Program .... -2.0V to +14.0V(2,3) VCC Supply Voltage with Respect to GND..............-2.0V to +7.0V(2) Output Short Circuit Current ................... 100 mA (4)
NOTICE: This datasheet contains preliminary information on new products in production. Do not finalize a design with this information. Revised information will be published when the product is available. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a design.
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* WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may effect device reliability.
NOTES:
1. 2. Operating temperature is for commercial product defined by this specification. Minimum DC voltage is -0.5V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <20 ns. Maximum DC voltage on input/output pins is VCC + 0.5V which, during transitions, may overshoot to VCC + 2.0V for periods <20 ns. Maximum DC voltage on VPP may overshoot to +14.0V for periods <20 ns. Maximum DC voltage on RP# or A9 may overshoot to 13.5V for periods <20 ns. Output shorted for no more than one second. No more than one output shorted at a time.
3.
4.
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5.0
Symbol TA VCC Parameter Operating Temperature 3.3V VCC Supply Voltage ( 0.3V) 5V VCC Supply Voltage (10%) 5V VCC Supply Voltage (5%)
4-MBIT SmartVoltage BOOT BLOCK FAMILY
COMMERCIAL OPERATING CONDITIONS
Table 10. Commercial Temperature and VCC Operating Conditions Notes Min 0 3.0 1 2 4.50 4.75 Max +70 3.6 5.50 5.25 Units C Volts Volts Volts
NOTES: 1. 10% VCC specifications apply to the 60 ns, 80 ns and 120 ns product versions in their standard test configuration. 2. 5% VCC specifications apply to the 60 ns version in its high-speed test configuration.
5.1
Applying VCC Voltages
When applying VCC voltage to the device, a delay may be required before initiating device operation, depending on the VCC ramp rate. If VCC ramps slower than 1V/100 s (0.01 V/s) then no delay is VCC Ramp Rate 1V/100 s > 1V/100 s No delay required.
required. If VCC ramps faster than 1V/100 s (0.01 V/s), then a delay of 2 s is required before initiating device operation. RP# = GND is recommended during power-up to protect against spurious write signals when VCC is between VLKO and VCCMIN. Required Timing
A delay time of 2 s is required before any device operation is initiated, including read operations, command writes, program operations, and erase operations. This delay is measured beginning from the time VCC reaches VCCMIN (3.0V for 3.3 0.3V operation; and 4.5V for 5V operation).
NOTES: 1. These requirements must be strictly followed to guarantee all other read and write specifications. 2. To switch between 3.3V and 5V operation, the system should first transition VCC from the existing voltage range to GND, and then to the new voltage. Any time the VCC supply drops below VCCMIN, the chip may be reset, aborting any operations pending or in progress. 3. These guidelines must be followed for any VCC transition from GND.
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29
4-MBIT SmartVoltage BOOT BLOCK FAMILY
5.2
DC Characteristics
Table 11. DC Characteristics (Commercial) Prod BV-60 BV-80 BV-120 3.3 0.3V Typ Max 1.0 10 0.4 1.5 0.8 5V 10% Typ Max 1.0 10 2.0 A A mA Unit
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Test Conditions VCC = VCC Max VIN = VCC or GND VCC = VCC Max VIN = VCC or GND VCC = VCC Max CE# = RP# = BYTE# = WP# = VIH VCC = VCC Max CE# = RP# = VCC 0.2V VCC = VCC Max VIN = VCC or GND RP# = GND 0.2V CMOS INPUTS VCC = VCC Max CE# = GND, OE# = VCC f = 10 MHz (5V) 5 MHz (3.3V) IOUT = 0 mA, Inputs = GND 0.2V or VCC 0.2V TTL INPUTS VCC = VCC Max CE# = VIL, OE# = VIH f = 10 MHz (5V) 5 MHz (3.3V) IOUT = 0 mA, Inputs = VIL or VIH VPP = VPPH1 (at 5V) Program in Progress VPP = VPPH2 (at 12V) Program in Progress VPP = VPPH1 (at 5V) Block Erase in Progress VPP = VPPH2 (at 12V) Block Erase in Progress 110 50 130 A
Sym
Parameter
VCC Note
IIL ILO ICCS
Input Load Current Output Leakage Current VCC Standby Current
1 1 1,3
60
ICCD
VCC Deep Power-Down Current VCC Read Current for Word or Byte
1
0.2
8
0.2
8
A
ICCR
1,5,6
15
30
50
60
mA
15
30
55
65
mA
ICCW
VCC Program Current for Word or Byte
1,4
13 10
30 25 30 25
30 30 18 18
50 45 35 30
mA mA mA mA
ICCE
VCC Erase Current
1,4
13 10
30
PRELIMINARY
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Sym ICCES IPPS IPPD IPPR IPPW
4-MBIT SmartVoltage BOOT BLOCK FAMILY
Table 11. DC Characteristics (Commercial) (Continued) Prod BV-60 BV-80 BV-120 3.3 0.3V Typ 3 0.5 0.2 50 13 8 Max 8.0 15 5.0 200 30 25 30 25 200 5V 10% Typ 5 0.5 0.2 30 13 8 10 5 30 Max 10 10 5.0 200 25 20 20 15 200 A mA mA A A A mA CE# = VIH Block Erase Suspend VPP < VPPH2 RP# = GND 0.2V VPP VPPH2 VPP = VPPH1 (at 5V) Program in Progress VPP = VPPH2 (at 12V) Program in Progress VPP = VPPH1 (at 5V) Block Erase in Progress VPP = VPPH2 (at 12V) Block Erase in Progress VPP = VPPH Block Erase Suspend in Progress RP# = VHH A9 = VID Unit Test Conditions
Parameter
VCC Note
VCC Erase Suspend Current VPP Standby Current VPP Deep Power-Down Current VPP Read Current VPP Program Current for Word or Byte
1,2 1 1 1 1,4
IPPE
VPP Erase Current
1,4
13 8
IPPES
VPP Erase Suspend Current RP# Boot Block Unlock Current A9 Intelligent Identifier Current
1
50
IRP# IID
1,4 1,4
500 500
500 500
A A
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4-MBIT SmartVoltage BOOT BLOCK FAMILY
Table 11. DC Characteristics (Commercial) (Continued) Prod BV-60 BV-80 BV-120 3.3 0.3V Min 11.4 -0.5 2.0 Max 12.6 0.8 VCC + 0.5V 0.45 2.4 0.85 x VCC VCC- 0.4V VPPLK VPP Lock-Out Voltage VPPH1 VPP (Prog/Erase Operations) VPPH2 VPP (Prog/Erase Operations) VLKO VHH VCC Erase/Prog Lock Voltage RP# Unlock Voltage 8 3 0.0 4.5 11.4 2.0 11.4 12.6 1.5 5.5 12.6 2.4 0.85 x VCC VCC- 0.4V 0.0 4.5 11.4 2.0 11.4 12.6 1.5 5.5 12.6 5V 10% Min 11.4 -0.5 2.0 Max 12.6 0.8 VCC + 0.5V 0.45 V V V V V V V V V V V V Unit
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Test Conditions VCC = VCC Min IOL = 5.8 mA VCC = VCC Min IOH = -2.5 mA VCC = VCC Min IOH = -2.5 mA VCC = VCC Min IOH = -100 A Total Write Protect VPP at 5V VPP at 12V
Sym
Parameter
VCC Note
VID VIL VIH VOL VOH1 VOH2
A9 Intelligent Identifier Voltage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage (TTL) Output High Voltage (CMOS)
Boot Block Unlock
Table 12. Capacitance (TA = 25C, f = 1 MHz) Symbol CIN COUT Parameter Input Capacitance Output Capacitance Note 4 4, 7 Typ 6 10 Max 8 12 Unit pF pF Conditions VIN = 0V VOUT = 0V
NOTES: 1. All currents are in RMS unless otherwise noted. Typical values at VCC = 5.0V, T = +25C. These currents are valid for all product versions (packages and speeds). 2. ICCES is specified with the device deselected. If the device is read while in erase suspend mode, current draw is the sum of ICCES and ICCR. 3. Block erases and word/byte writes are inhibited when VPP = VPPLK, and not guaranteed in the range between VPPH1 and VPPLK. 4. Sampled, not 100% tested. 5. Automatic Power Savings (APS) reduces ICCR to less than 1 mA typical, in static operation. 6. CMOS Inputs are either VCC 0.2V or GND 0.2V. TTL Inputs are either VIL or VIH. 7. For the 28F004B, address pin A10 follows the COUT capacitance numbers. 8. For all BV/CV parts, VLKO = 2.0V for both 3.3V and 5V operations.
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3.0 INPUT 0.0 1.5
4-MBIT SmartVoltage BOOT BLOCK FAMILY
TEST POINTS
1.5
OUTPUT
NOTE: AC test inputs are driven at 3.0V for a logic "1" and 0.0V for a logic "0." Input timing begins, and output timing ends, at 1.5V. Input rise and fall times (10% to 90%) <10 ns.
0530_12
Figure 12. 3.3V Inputs and Measurement Points
2.4 INPUT 0.45
2.0 TEST POINTS 0.8
2.0 OUTPUT 0.8
NOTE: AC test inputs are driven at VOH (2.4 VTTL) for a logic "1" and VOL (0.45 VTTL) for a logic "0." Input timing begins at VIH (2.0 VTTL) and VIL (0.8 VTTL) . Output timing ends at VIH and VIL. Input rise and fall times (10% to 90%) <10 ns.
0530_13
Figure 13. 5V Inputs and Measurement Points
VCC
Test Configuration Component Values Test Configuration
R1
CL (pF) R1 () R2 () 50 100 30 990 580 580 770 390 390
3.3V Standard Test 5V Standard Test
DEVICE UNDER TEST
OUT
5V High-Speed Test
CL
NOTE: CL includes jig capacitance.
R2
0530_14
NOTE: See table for component values.
Figure 14. Test Configuration
PRELIMINARY
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4-MBIT SmartVoltage BOOT BLOCK FAMILY
5.3
AC Characteristics
Table 13. AC Characteristics: Read Only Operations (Commercial) Prod BV-60 3.3 0.3V(5) 50 pF Min 110 110 2 110 0.8 2 3 3 3 3 3 0 0 25 0 0 25 0 20 0 65 0 20 0 Max 5V 5%(6) 30 pF Min 60 60 60 0.45 30 0 Max
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5V 10%(7) 100 pF Min 70 70 70 0.45 35 Max ns ns ns s ns ns 20 ns ns 20 ns ns Unit
Sym
Parameter
VCC Load Note
tAVAV tAVQV tELQV tPHQV tGLQV tELQX tEHQZ tGLQX tGHQZ tOH
Read Cycle Time Address to Output Delay CE# to Output Delay RP# to Output Delay OE# to Output Delay CE# to Output in Low Z CE# to Output in High Z OE# to Output in Low Z OE# to Output in High Z Output Hold from Address, CE#, or OE# Change, Whichever Occurs First CE# Low to BYTE# High or Low Address to BYTE# High or Low BYTE# to Output Delay BYTE# Low to Output in High Z Reset Pulse Width Low RP# Low to Output High Z
tELFL tELFH tAVFL tFLQV tFHQV tFLQZ tPLPH tPLQZ
3 3 3,4 3 8
0 5 110 45 150 150
0 5 60 20 60 60
0 5 70 25 60 60
ns ns ns ns ns ns
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Sym Parameter VCC Load Notes tAVAV tAVQV tELQV tPHQV tGLQV tELQX tEHQZ tGLQX tGHQZ tOH Read Cycle Time Address to Output Delay CE# to Output Delay RP# to Output Delay OE# to Output Delay CE# to Output in Low Z CE# to Output in High Z OE# to Output in Low Z OE# to Output in High Z Output Hold from Address, CE#, or OE# Change, Whichever Occurs First CE# Low to BYTE# High or Low Address to BYTE# High or Low BYTE# to Output Delay BYTE# Low to Output in High Z Reset Pulse Width Low RP# Low to Output High Z 2 3 3 3 3 3 0 0 0 2 3.3 Min 150
4-MBIT SmartVoltage BOOT BLOCK FAMILY
Table 13. AC Characteristics: Read Only Operations (Commercial) (Continued) BV-80 0.3V(5) 5V 10%(7) BV-120 3.3 0.3V(5) 5V 10%(7) Unit 50 pF Min 180 80 80 0.45 40 0 25 0 25 0 20 0 20 0 25 0 0 25 0 20 180 180 0.8 90 0 20 Max 100 pF Min 120 120 120 0.45 40 Max ns ns ns s ns ns ns ns ns ns
50 pF Max
100 pF Min 80 Max
150 150 0.8 90
tELFL tELFH tAVFL tFLQV tFHQV tFLQZ tPLPH tPLQZ
3 3 3,4 3 8
0 5 150 60 150 150
0 5 80 30 60 60
0 5 180 60 150 150
0 5 120 30 60 60
ns ns ns ns ns
NOTES: 1. See AC Input/Output Reference Waveform for timing measurements. 2. OE# may be delayed up to tCE-tOE after the falling edge of CE# without impact on tCE. 3. Sampled, but not 100% tested. 4. tFLQV, BYTE# switching low to valid output delay will be equal to tAVQV, measured from the time DQ15/A-1 becomes valid. 5. See Test Configurations (Figure 14), 3.3V Standard Test component values. 6. See Test Configurations (Figure 14), 5V High-Speed Test component values. 7. See Test Configurations (Figure 14), 5V Standard Test component values. 8. The specification tPLPH is the minimum time RP# must be held low to produce a valid reset of the device.
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35
4-MBIT SmartVoltage BOOT BLOCK FAMILY
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Data Valid Standby t AVAV
ADDRESSES (A)
VIH VIL VIH
Device and Address Selection Address Stable
CE# (E)
OE# (G)
VIL VIH VIL VIH
VIL
t EHQZ
tGHQZ t GLQX
High Z
WE# (W)
t GLQV t ELQV
Valid Output
t OH
High Z
VOH DATA (D/Q) VOL
RP#(P)
t ELQX t AVQV t PHQV
VIH
VIL
0530_15
Figure 15. AC Waveforms for Read Operations
Device Address Selection Address Stable t AVAV t EHQZ Data Valid
VIH ADDRESSES (A) VIL CE# (E) VIH VIL OE# (G) VIH VIL BYTE# (F) VIH VIL
Standby
t AVFL t ELFL
t GHQZ
VOH DATA (D/Q)
(DQ0-DQ7)
t GLQV t ELQV t GLQX High Z t ELQX t AVQV High Z t FLQZ High Z
Data Output on DQ15 Data Output on DQ8-DQ14 Data Output on DQ0-DQ7
t OH
Data Output on DQ0-DQ7
High Z
VOL DATA (D/Q)
(DQ8-DQ14)
VOH VOL VOH
High Z t AVQV
Address Input
(DQ15/A-1)
High Z
VOL
0530_16
Figure 16. BYTE# Timing Diagram for Read Operations
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PRELIMINARY
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Prod Sym Parameter VCC Load Note tAVAV tPHWL tELWL tPHHWH tVPWH tAVWH tDVWH tWLWH tWHDX tWHAX tWHEH tWHWL tWHQV1 tWHQV2 tWHQV3 tWHQV4 tQVVL tQVPH tPHBR Write Cycle Time RP# Setup to WE# Going Low CE# Setup to WE# Going Low Boot Block Lock Setup to WE# Going High VPP Setup to WE# Going High Address Setup to WE# Going High Data Setup to WE# Going High WE# Pulse Width Data Hold Time from WE# High Address Hold Time from WE# High CE# Hold Time from WE# High WE# Pulse Width High Duration of Word/Byte Program Duration of Erase (Boot) Duration of Erase (Parameter) Duration of Erase (Main) VPP Hold from Valid SRD RP# VHH Hold from Valid SRD Boot-Block Lock Delay 2,5 2,5,6 2,5 2,5 5,8 6,8 7,8 4 3 6,8 5,8 3 4
4-MBIT SmartVoltage BOOT BLOCK FAMILY
Table 14. AC Characteristics: WE#-Controlled Write Operations (1) (Commercial) BV-60 3.3 0.3V(9) 5V 5%(10) 30 pF
Min Max
5V 10%(10) 100 pF
Min Max
Unit
50 pF
Min Max
110 0.8 0 200 200 90 90 90 0 0 0 20 6 0.3 0.3 0.6 0 0 200
60 0.45 0 100 100 50 50 50 0 0 0 10 6 0.3 0.3 0.6 0 0 100
70 0.45 0 100 100 50 50 50 0 0 0 20 6 0.3 0.3 0.6 0 0 100
ns s ns ns ns ns ns ns ns ns ns ns s s s s ns ns ns
PRELIMINARY
37
4-MBIT SmartVoltage BOOT BLOCK FAMILY
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BV-80 BV-120 3.3 0.3V(9) 50 pF
Min Max
(9)
Table 14. AC Characteristics: WE#-Controlled Write Operations (1) (Commercial) (Continued) Prod Sym Parameter VCC Load Notes tAVAV tPHWL tELWL tPHHWH tVPWH tAVWH tDVWH tWLWH tWHDX tWHAX tWHEH tWHWL tWHQV1 tWHQV2 tWHQV3 tWHQV4 tQVVL tQVPH tPHBR Write Cycle Time RP# Setup to WE# Going Low CE# Setup to WE# Going Low Boot Block Lock Setup to WE# Going High VPP Setup to WE# Going High Address Setup to WE# Going High Data Setup to WE# Going High WE# Pulse Width Data Hold Time from WE# High Address Hold Time from WE# High CE# Hold Time from WE# High WE# Pulse Width High Word/Byte Program Time Erase Duration (Boot) Erase Duration (Param) Erase Duration (Main) VPP Hold from Valid SRD RP# VHH Hold from Valid SRD Boot-Block Lock Delay 2,5 2,5,6 2,5 2,5 5,8 6,8 7,8 4 3 6,8 5,8 3 4 3.3 0.3V 50 pF
Min Max
5V10%(11) 100 pF
Min Max
5V10%(11) Unit 100 pF
Min Max
150 0.8 0 200 200 120 120 120 0 0 0 30 6 0.3 0.3 0.6 0 0 200
80 0.45 0 100 100 50 50 50 0 0 0 30 6 0.3 0.3 0.6 0 0 100
180 0.8 0 200 200 150 150 150 0 0 0 30 6 0.3 0.3 0.6 0 0 200
120 0.45 0 100 100 50 50 50 0 0 0 30 6 0.3 0.3 0.6 0 0 100
ns s ns ns ns ns ns ns ns ns ns ns s s s s ns ns ns
38
PRELIMINARY
NOTES: 1. Read timing characteristics during write and erase operations are the same as during read-only operations. Refer to AC characteristics during read mode. 2. The on-chip WSM completely automates program/erase operations; program/erase algorithms are now controlled internally which includes verify and margining operations. 3. Refer to command definition table for valid AIN. (Table 7) 4. Refer to command definition table for valid DIN. (Table 7) 5. Program/erase durations are measured to valid SRD data (successful operation, SR.7 = 1). 6. For boot block program/erase, RP# should be held at VHH or WP# should be held at VIH until operation completes successfully. 7. Time tPHBR is required for successful locking of the boot block. 8. Sampled, but not 100% tested. 9. See Test Configurations (Figure 14), 3.3V Standard Test component values. 10. See Test Configurations (Figure 14), 5V High-Speed Test component values. 11. See Test Configurations (Figure 14), 5V Standard Test component values.
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4-MBIT SmartVoltage BOOT BLOCK FAMILY
VIH
ADDRESSES (A)
1
2
3
4
5
6
CE# (E)
VIL VIH
VIL t VIH ELWL VIL VIH
AIN
t AVAV
AIN
tAVWH t WHAX
tWHEH t WHWL
t WLWH t DVWH t WHDX
OE# (G)
t WHQV1,2,3,4
WE# (W)
VIL
VIH
DATA (D/Q)
High Z
VIL
6.5V RP# (P)
DIN
DIN
t PHHWH
Valid SRD
DIN
tQVPH
VHH
t PHWL
VIH
VIL
VIH
WP#
VIL
t VPWH
VPPH 2 VPPH 1 V (V) V PP PPLK
t QVVL
VIL
0530_17
NOTES: 1. VCC Power-Up and Standby. 2. Write Program or Erase Setup Command. 3. Write Valid Address and Data (Program) or Erase Confirm Command. 4. Automated Program or Erase Delay. 5. Read Status Register Data. 6. Write Read Array Command.
Figure 17. AC Waveforms for Write Operations (WE#-Controlled Writes)
PRELIMINARY
39
4-MBIT SmartVoltage BOOT BLOCK FAMILY
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BV-60 3.3 0.3V(9) 5V 5%(10) 30 pF Min 60 0.45 0 100 100 50 50 50 0 0 0 10 6 0.3 0.3 0.6 0 0 200 100 Max 5V 10%(11) 100 pF Min 70 0.45 0 100 100 50 50 50 0 0 0 20 6 0.3 0.3 0.6 0 0 100 Max ns s Unit 50 pF Min 110 0.8 0 Max ns ns ns ns ns ns ns ns ns ns s s s s ns ns ns 200 200 90 90 90
Table 15. AC Characteristics: CE#-Controlled Write Operations (1,12) (Commercial) Prod Sym Parameter VCC Load Note tAVAV tPHEL tWLEL tPHHEH tVPEH tAVEH tDVEH tELEH tEHDX tEHAX tEHWH tEHEL tEHQV1 tEHQV2 tEHQV3 tEHQV4 tQVVL tQVPH tPHBR Write Cycle Time RP# High Recovery to CE# Going Low WE# Setup to CE# Going Low Boot Block Lock Setup to CE# Going High VPP Setup to CE# Going High Address Setup to CE# Going High Data Setup to CE# Going High CE# Pulse Width Data Hold Time from CE# High Address Hold Time from CE# High WE # Hold Time from CE# High CE# Pulse Width High Duration of Word/Byte Programming Operation Erase Duration (Boot) Erase Duration (Param) Erase Duration(Main) VPP Hold from Valid SRD RP# VHH Hold from Valid SRD Boot-Block Lock Delay 2,5 2,5,6 2,5 2,5 5,8 6,8 7,8 4 3 6,8 5,8 3 4
0 0 0 20 6 0.3 0.3 0.6 0 0
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Prod Sym Parameter VCC Load Notes tAVAV tPHEL tWLEL tPHHEH tVPEH tAVEH tDVEH tELEH tEHDX tEHAX tEHWH tEHEL tEHQV1 tEHQV2 tEHQV3 tEHQV4 tQVVL tQVPH tPHBR Write Cycle Time RP# High Recovery to CE# Going Low WE# Setup to CE# Going Low Boot Block Lock Setup to CE# Going High VPP Setup to CE# Going High Address Setup to CE# Going High Data Setup to CE# Going High CE# Pulse Width Data Hold Time from CE# High Address Hold Time from CE# High WE # Hold Time from CE# High CE# Pulse Width High Duration of Word/Byte Programming Operation Erase Duration (Boot) Erase Duration (Param) Erase Duration(Main) VPP Hold from Valid SRD RP# VHH Hold from Valid SRD Boot-Block Lock Delay 2,5 2,5,6 2,5 2,5 5,8 6,8 7,8 4 3 6,8 5,8 3 4 3.3 Min 150 0.8 0 200 200 120 120 120 0 0 0 30 6 0.3 0.3 0.6 0 0
4-MBIT SmartVoltage BOOT BLOCK FAMILY
Table 15. AC Characteristics: CE#-Controlled Write Operations (1,12) (Commercial) (Continued) BV-80 0.3V(9) 5V10%(11) 100 pF Min 80 0.45 0 100 100 50 50 50 0 0 0 30 6 0.3 0.3 0.6 0 0 200 100 Max BV-120 3.3 0.3V(9) 50 pF Min 180 0.8 0 200 200 150 150 150 0 0 0 30 6 0.3 0.3 0.6 0 0 200 Max 5V10%(11) Unit 100 pF Min 120 0.45 0 100 100 50 50 50 0 0 0 30 6 0.3 0.3 0.6 0 0 100 Max ns s ns ns ns ns ns ns ns ns ns ns s s s s ns ns ns
50 pF Max
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4-MBIT SmartVoltage BOOT BLOCK FAMILY
NOTES: See WE# Controlled Write Operations for notes 1 through 11. 12. Chip-Enable controlled writes: write operations are driven by the valid combination of CE# and WE# in systems where CE# defines the write pulse-width (within a longer WE# timing waveform), all set-up, hold and inactive WE# times should be measured relative to the CE# waveform.
1 2 AIN t AVAV 3 AIN t AVEH t EHAX 4 5 6
E
VIH
ADDRESSES (A)
VIL VIH
WE# (W)
VIL
OE# (G)
VIH VIL VIH
t WLEL t
tEHWH t EHQV1,2,3,4
EHEL
CE# (E)
VIL VIH
DATA (D/Q)
High Z
t ELEH t DVEH t EHDX DIN DIN tPHHEH
Valid SRD
VIL
6.5V RP# (P)
DIN
VHH VIH VIL VIH
t PHEL
tQVPH
WP#
VIL t VPEH t QVVL
VPPH 2 VPPH1 V (V) V PP PPLK VIL
0530_18
NOTES: 1. VCC Power-Up and Standby. 2. Write Program or Erase Setup Command. 3. Write Valid Address and Data (Program) or Erase Confirm Command. 4. Automated Program or Erase Delay. 5. Read Status Register Data. 6. Write Read Array Command.
Figure 18. Alternate AC Waveforms for Write Operations (CE#-Controlled Writes)
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VPP VCC Parameter Boot/Parameter Block Erase Time Main Block Erase Time Main Block Program Time (Byte) Main Block Program Time (Word) Byte Program Time(4) Word Program Time(4) 3.3 0.3V Typ 0.84 2.4 1.7 1.1 10 13 Max 7 14
4-MBIT SmartVoltage BOOT BLOCK FAMILY
Table 16. Erase and Program Timings (Commercial T A = 0C to +70C) 5V 10% 5V 10% Typ 0.8 1.9 1.8 0.9 10 13 Max 7 14 12V 5% 3.3 0.3V Typ 0.44 1.3 1.6 0.8 8 8 Max 7 14 5V 10% Typ 0.34 1.1 1.2 0.6 8 8 Max 7 14 Unit s s s s s s
NOTES: 1. All numbers are sampled, not 100% tested. 2. Max erase times are specified under worst case conditions. The max erase times are tested at the same value independent of VCC and VPP. See Note 3 for typical conditions. 3. Typical conditions are +25C with VCC and VPP at the center of the specifed voltage range. Production programming using VCC = 5.0V, VPP = 12.0V typically results in a 60% reduction in programming time. 4. Contact your Intel field representative for more information.
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6.0
EXTENDED OPERATING CONDITIONS
Table 17. Extended Temperature and VCC Operating Conditions
E
Min -40 1 1 2 2.7 3.0 4.50 Max +85 3.6 3.6 5.50 Units C Volts Volts Volts
Symbol TA VCC
Parameter Operating Temperature 2.7V-3.6V VCC Supply Voltage 3.3V VCC Supply Voltage ( 0.3V) 5V VCC Supply Voltage (10%)
Notes
NOTES: 1. AC specifications are valid at both voltage ranges. See DC Characteristics tables for voltage range-specific specifications. 2. 10% VCC specifications apply to 80 ns and 120 ns versions in their standard test configuration.
6.1
Applying VCC Voltages
When applying VCC voltage to the device, a delay may be required before initiating device operation, depending on the VCC ramp rate. If VCC ramps slower than 1V/100 s (0.01 V/s) then no delay is VCC Ramp Rate 1V/100 s > 1V/100 s No delay required.
required. If VCC ramps faster than 1V/100 s (0.01 V/s), then a delay of 2 s is required before initiating device operation. RP# = GND is recommended during power-up to protect against spurious write signals when VCC is between VLKO and VCCMIN. Required Timing
A delay time of 2 s is required before any device operation is initiated, including read operations, command writes, program operations, and erase operations. This delay is measured beginning from the time VCC reaches VCCMIN (2.7V for 2.7V-3.6V operation, 3.0V for 3.3 0.3V operation; and 4.5V for 5V operation).
NOTES: 1. These requirements must be strictly followed to guarantee all other read and write specifications. 2. To switch between 3.3V and 5V operation, the system should first transition VCC from the existing voltage range to GND, and then to the new voltage. Any time the VCC supply drops below VCCMIN, the chip may be reset, aborting any operations pending or in progress. 3. These guidelines must be followed for any VCC transition from GND.
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6.2
Sym IIL ILO ICCS
4-MBIT SmartVoltage BOOT BLOCK FAMILY
DC Characteristics
Table 18. DC Characteristics: Extended Temperature Operation Prod Parameter VCC Notes TBE-120 2.7V-3.6V Typ Max 1.0 10 TBV-80 3.3 0.3V Typ Max 1.0 10 TBV-80 TBE-120 5V 10% Typ Max 1.0 10 A A VCC = VCCMax VIN = VCC or GND VCC = VCC Max VIN = VCC or GND CMOS Levels VCC = VCC Max CE# = RP# = WP# = VCC 0.2V 0.4 1.5 0.4 1.5 0.8 2.5 mA TTL Levels VCC = VCC Max CE# = RP# = BYTE# = VIH Unit Test Conditions
Input Load Current Output Leakage Current VCC Standby Current
1 1
1,3
50
110
60
110
70
150
A
ICCD
ICCR
VCC Deep PowerDown Current VCC Read Current for Word or Byte
1
0.2
8
0.2
8
0.2
8
A
VCC = VCC Max VIN = VCC or GND RP# = GND 0.2V CMOS INPUTS VCC = VCC Max CE = VIL f = 10 MHz (5V) 5 MHz (3.3V) IOUT = 0 mA Inputs = GND 0.2V or VCC 0.2V TTL INPUTS VCC = VCC Max CE# = VIL f = 10 MHz (5V), 5 MHz (3.3V) IOUT = 0 mA Inputs = VIL or VIH
1,5,6
14
30
15
30
50
65
mA
14
30
15
30
55
70
mA
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Table 18. DC Characteristics: Extended Temperature Operation (Continued) Prod Sym Parameter VCC Notes ICCW VCC Program Current for Word or Byte ICCE VCC Erase Current 1,4 1,4 TBE-120 2.7V-3.6V Typ 8 Max 30 TBV-80 3.3 0.3V Typ 13 Max 30 TBV-80 TBE-120 5V 10% Typ 30 Max 50 mA Unit
E
Test Conditions
VPP = VPPH1 (at 5V) Program in Progress VPP = VPPH2 (at 12V) Program in Progress VPP = VPPH1 (at 5V) Erase in Progress VPP = VPPH2 (at 12V) Erase in Progress CE# = VIH VPP = VPPH1 (at 5V) Block Erase Suspend VPP < VPPH2
9 12 9
25 30 25 8.0
10 13 10 3
25 30 25 8.0
30 22 18 5
45 45 40 12.0
mA mA mA mA
ICCES
VCC Erase Suspend Current VPP Standby Current VPP Deep PowerDown Current VPP Read Current VPP Program Current for Word/Byte
1,2
2.5
IPPS
1
5
15
5
15
5
15
A
IPPD
1
0.2
10
0.2
10
0.2
10
A
RP# = GND 0.2V
IPPR IPPW
1 1,4
50 13 8
200 30 25
50 13 8
200 30 25
50 13 8
200 30 25
A mA mA
VPP VPPH2 VPP = VPPH1 (at 5V) Program in Progress VPP = VPPH2 (at 12V) Program in Progress
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Sym IPPE IPPES IRP#
4-MBIT SmartVoltage BOOT BLOCK FAMILY
Table 18. DC Characteristics: Extended Temperature Operation (Continued) Prod TBE-120 2.7V-3.6V Typ 13 Max 30 TBV-80 3.3 0.3V Typ 13 Max 30 TBV-80 TBE-120 5V 10% Typ 15 Max 25 mA VPP = VPPH1 (at 5V) Block Erase in Progress VPP = VPPH2 (at 12V) Block Erase in Progress VPP = VPPH Block Erase Suspend in Progress RP# = VHH VPP = 12V Unit Test Conditions
Parameter
VCC Notes
VPP Erase Current
1,4
8
25
8
25
10
20
mA
VPP Erase Suspend Current RP# Boot Block Unlock Current A9 Intelligent Identifier Current
1
50
200
50
200
50
200
A
1,4
500
500
500
A
IID
1,4
500
500
500
A
A9 = VID
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4-MBIT SmartVoltage BOOT BLOCK FAMILY
Table 18. DC Characteristics: Extended Temperature Operation (Continued) Prod Sym Parameter VCC Notes VID A9 Intelligent Identifier Voltage Input Low Voltage Input High Voltage Output Low Voltage TBE-120 2.7V-3.6V Min 11.4 Max 12.6 TBV-80 3.3 0.3V Min 11.4 Max 12.6 TBV-80 TBE-120 5V 10% Min 11.4 Max 12.6 V Unit
E
Test Conditions
VIL VIH
-0.5 2.0
0.8 VCC 0.5V 0.45
-0.5 2.0
0.8 VCC 0.5V 0.45
-0.5 2.0
0.8 VCC 0.5V 0.45
V V
VOL
V
VCC = VCC Min IOL = 5.8 mA (5V) 2 mA (3.3V) VPP = 12V VCC = VCC Min IOH = -2.5 mA
VOH1
Output High Voltage (TTL) Output High Voltage (CMOS)
2.4
2.4
2.4
V
VOH2
0.85 x VCC VCC- 0.4V
0.85 x VCC VCC- 0.4V 1.5 0.0 1.5
0.85 x VCC VCC- 0.4V 0.0 1.5
V
VCC = VCC Min IOH = -2.5 mA VCC = VCC Min IOH = -100 A Complete Write Protection VPP at 5V VPP at 12V
V
VPPLK VPP Lock-Out Voltage VPP during VPPH1 Prog/Erase Operations VPPH2 VLKO VCC Erase/Write Lock Voltage RP# Unlock Voltage
3
0.0
V
4.5 11.4 8 2.0
5.5 12.6
4.5 11.4 2.0
5.5 12.6
4.5 11.4 2.0
5.5 12.6
V V V
VHH
11.4
12.6
11.4
12.6
11.4
12.6
V
VPP = 12V Boot Block Write/ Erase
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Symbol CIN COUT Parameter
4-MBIT SmartVoltage BOOT BLOCK FAMILY
Table 19. Capacitance (TA = 25 C, f = 1 MHz) Note 4 4 Typ 6 10 Max 8 12 Unit pF pF Conditions VIN = 0V VOUT = 0V
Input Capacitance Output Capacitance
NOTES: 1. All currents are in RMS unless otherwise noted. Typical values at VCC = 5.0V, T = +25C. These currents are valid for all product versions (packages and speeds). 2. ICCES is specified with device de-selected. If device is read while in erase suspend, current draw is sum of I CCES and ICCR. 3. Block erases and word/byte programs inhibited when VPP = VPPLK, and not guaranteed in the range between VPPH1 and VPPLK. 4. Sampled, not 100% tested. 5. Automatic Power Savings (APS) reduces ICCR to less than 1 mA typical, in static operation. 6. CMOS Inputs are either VCC 0.2V or GND 0.2V. TTL Inputs are either VIL or VIH. 7. For the 28F004B address pin A10 follows the COUT capacitance numbers. 8. For all BV/CV/BE/CE parts, VLKO = 2.0V for 2.7V, 3.3V and 5.0V operations.
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1.35 OUTPUT
0530_19
2.7 INPUT 0.0
NOTE: AC test inputs are driven at 2.7V for a logic "1" and 0.0V for a logic "0." Input timing begins, and output timing ends, at 1.35V. Input rise and fall times (10% to 90%) <10 ns.
1.35
TEST POINTS
Figure 19. 2.7V-3.6V Input Range and Measurement Points
3.0 INPUT 0.0
0530_12
1.5
TEST POINTS
1.5
OUTPUT
NOTE: AC test inputs are driven at 3.0V for a logic "1" and 0.0V for a logic "0." Input timing begins, and output timing ends, at 1.5V. Input rise and fall times (10% to 90%) <10 ns.
Figure 20. 3.3V Input Range and Measurement Points
2.4 INPUT 0.45
2.0 TEST POINTS 0.8
2.0 OUTPUT 0.8
0530_13
NOTE: AC test inputs are driven at VOH (2.4 VTTL) for a logic "1" and VOL (0.45 VTTL) for a logic "0." Input timing begins at VIH (2.0 VTTL) and VIL (0.8 VTTL). Output timing ends at VIH and VIL. Input rise and fall times (10% to 90%) < 10 ns.
Figure 21. 5V Input Range and Measurement Points
VCC
Test Configuration Component Values Test Configuration
R1
CL (pF) R1 () R2 () 50 100 990 580 770 390
2.7V and 3.3V Standard Test 5V Standard Test
OUT
DEVICE UNDER TEST
NOTE: CL includes jig capacitance.
CL
R2
0530_14
NOTE: See table for component values.
Figure 22. Test Configuration 50
PRELIMINARY
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6.3
Sym tAVAV tAVQV tELQV tPHQV tGLQV tELQX tEHQZ tGLQX tGHQZ tOH
4-MBIT SmartVoltage BOOT BLOCK FAMILY
AC Characteristics
Table 20. AC Characteristics: Read Only Operations(1) (Extended Temperature) Prod Parameter VCC Load Notes Read Cycle Time Address to Output Delay CE# to Output Delay RP# to Output Delay OE# to Output Delay CE# to Output in Low Z CE# to Output in High Z OE# to Output in Low Z OE# to Output in High Z Output Hold from Address, CE#, or OE# Change, Whichever Occurs First CE# Low to BYTE# High or Low Address to BYTE# High or Low BYTE# to Output Delay BYTE# Low to Output in High Z Reset Pulse Width Low RP# Low to Output High Z 2 3 3 3 3 3 0 0 25 0 0 25 0 25 0 2 TBE-120 2.7V-3.6V(5) 50 pF Min 120 120 120 0.8 65 0 25 0 20 Max TBV-80 3.3 0.3V(5) 50 pF Min 110 110 110 0.8 65 0 20 Max TBV-80 TBE-120 5V10%(6) 100 pF Min 80 80 80 0.45 40 Max ns ns ns s ns ns ns ns ns ns Unit
tELFL tELFH tAVFL tFLQV tFHQV tFLQZ tPLPH tPLQZ
3 3 3,4 3 7 150 0
5 0 120 45 150 150
5 0 110 45 60 150
5
ns ns
80 30
ns ns ns
60
ns
NOTES: 1. See AC Input/Output Reference Waveform for timing measurements. 2. OE# may be delayed up to tCE-tOE after the falling edge of CE# without impact on tCE. 3. Sampled, but not 100% tested. 4. tFLQV, BYTE# switching low to valid output delay will be equal to tAVQV, measured from the time DQ15/A-1 becomes valid. 5. See Test Configurations (Figure 22), 2.7V-3.6V and 3.3 0.3V Standard Test component values. 6. See Test Configurations (Figure 22), 5V Standard Test component values. 7. The specification tPLPH is the minimum time RP# must be held low to produce a valid reset of the device.
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E
TBE-120 2.7V-3.6V(9) 50 pF Min 120 0.8 0 Max TBV-80 3.30.3V(9) 50 pF Min 110 0.8 0 200 200 90 70 90 0 0 0 20 6 0.3 0.3 0.6 0 0 200 200 Max TBV-80 TBE-120 5V10%(10) 100 pF Min 80 0.45 0 100 100 60 60 60 0 0 0 20 6 0.3 0.3 0.6 0 0 100 Max ns s ns ns ns ns ns ns ns ns ns ns s s s s ns ns ns Unit 200 200 90 70 90
Table 21. AC Characteristics: WE#-Controlled Write Operations(1) (Extended Temperature) Prod Sym Parameter VCC Load Notes tAVAV tPHWL tELWL tPHHWH tVPWH tAVWH tDVWH tWLWH tWHDX tWHAX tWHEH tWHWL tWHQV1 tWHQV2 tWHQV3 tWHQV4 tQVVL tQVPH tPHBR Write Cycle Time RP# High Recovery to WE# Going Low CE# Setup to WE# Going Low Boot Block Lock Setup to WE# Going High VPP Setup to WE# Going High Address Setup to WE# Going High Data Setup to WE# Going High WE# Pulse Width Data Hold Time from WE# High Address Hold Time from WE# High CE# Hold Time from WE# High WE# Pulse Width High Word/Byte Program Time Erase Duration (Boot) Erase Duration (Param) Erase Duration (Main) VPP Hold from Valid SRD RP# VHH Hold from Valid SRD Boot-Block Lock Delay 2,5,8 2,5, 6, 8 2,5,8 2,5,8 5,8 6,8 7,8 4 3 6,8 5,8 3 4
0 0 0 30 6 0.3 0.3 0.6 0 0
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PRELIMINARY
NOTES: 1. Read timing characteristics during program and erase operations are the same as during read-only operations. Refer to AC Characteristics during read mode. 2. The on-chip WSM completely automates program/erase operations; program/erase algorithms are now controlled internally which includes verify and margining operations. 3. Refer to command definition table for valid AIN. (Table 7) 4. Refer to command definition table for valid DIN. (Table 7) 5. Program/erase durations are measured to valid SRD data (successful operation, SR.7 = 1) 6. For boot block program/erase, RP# should be held at VHH or WP# should be held at VIH until operation completes successfully. 7. Time tPHBR is required for successful locking of the boot block. 8. Sampled, but not 100% tested. 9. See Test Configurations (Figure 22), 2.7V-3.6V and 3.3 0.3V Standard Test component values. 10. See Test Configurations (Figure 22), 5V Standard Test component values.
E
4-MBIT SmartVoltage BOOT BLOCK FAMILY
PRELIMINARY
53
4-MBIT SmartVoltage BOOT BLOCK FAMILY
E
TBE-120 2.7V-3.6V(9) 50 pF Min 120 0.8 0 Max TBV-80 3.3 0.3V(9) 50 pF Min 110 0.8 0 200 200 90 70 90 0 0 0 20 6 0.3 0.3 0.6 0 0 200 200 Max TBV-80 TBE-120 5V10%(10) 100 pF Min 80 0.45 0 100 100 60 60 60 0 0 0 20 6 0.3 0.3 0.6 0 0 100 Max ns s ns ns ns ns ns ns ns ns ns ns s s s s ns ns ns Unit 200 200 90
Table 22. AC Characteristics: CE#-Controlled Write Operations (1,11) (Extended Temperature) Prod Sym Parameter VCC Load Notes tAVAV tPHEL tWLEL tPHHEH tVPEH tAVEH tDVEH tELEH tEHDX tEHAX tEHWH tEHEL tEHQV1 tEHQV2 tEHQV3 tEHQV4 tQVVL tQVPH tPHBR Write Cycle Time RP# High Recovery to CE# Going Low WE# Setup to CE# Going Low Boot Block Lock Setup to CE# Going High VPP Setup to CE# Going High Address Setup to CE# Going High Data Setup to CE# Going High CE# Pulse Width Data Hold Time from CE# High Address Hold Time from CE# High WE# Hold Time from CE# High CE# Pulse Width High Word/Byte Program Time Erase Duration (Boot) Erase Duration (Param) Erase Duration (Main) VPP Hold from Valid SRD RP# VHH Hold from Valid SRD Boot-Block Lock Delay 2,5 2,5,6 2,5 2,5 5,8 6,8 7,8 4 3 3 4 6,8 5,8
70 90 0 0 0 20 6 0.3 0.3 0.6 0 0
NOTES: See WE# Controlled Write Operations for notes 1 through 10. 11. Chip-Enable controlled writes: write operations are driven by the valid combination of CE# and WE# in systems where CE# defines the write pulse-width (within a longer WE# timing waveform), all set-up, hold and inactive WE# times should be measured relative to the CE# waveform.
54
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VPP VCC Parameter Main Block Erase Time Main Block Program Time (Byte Mode) Main Block Program Time (Word Mode) Byte Program Time(4) Word Program Time(4)
4-MBIT SmartVoltage BOOT BLOCK FAMILY
Table 23. Erase and Program Timings (Extended T A = -40C to +85C) 5V 10% 2.7V-3.6V Typ 0.88 2.5 1.87 Max 7 14 3.3 0.3V Typ 0.84 2.4 1.7 Max 7 14 5V 10% Typ 0.8 1.9 1.4 Max 7 14 2.7V-3.6V Typ 0.46 1.36 1.76 Max 7 14 12V 5% 3.3 0.3V Typ 0.44 1.3 1.6 Max 7 14 5V 10% Typ 0.34 1.1 1.2 Max Unit 7 14 s s s
Boot/Parameter Block Erase Time
1.21
1.1
0.9
0.88
0.8
0.6
s
11 14.3
10 13
10 13
8.8 8.8
8 8
8 8
s s
NOTES: 1. All numbers are sampled, not 100% tested. 2. Max erase times are specified under worst case conditions. The max erase times are tested at the same value independent of VCC and VPP. See Note 3 for typical conditions. 3. Typical conditions are +25C with VCC and VPP at the center of the specifed voltage range. Production programming using VCC = 5.0V, VPP = 12.0V typically results in a 60% reduction in programming time. 4. Contact your Intel field representative for more information.
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55
4-MBIT SmartVoltage BOOT BLOCK FAMILY
APPENDIX A ORDERING INFORMATION
E
Access Speed(ns) BV/CV: VCC = 5V BE/CE: VCC = 2.7V T = Top Boot B = Bottom Boot Voltage Options (VPP/VCC) V = (5 or 12 / 3.3 or 5) E = (5 or 12 / 2.7 or 5)
T E 2 8 F 4 0 0 CV - T 8 0
Operating Temperature T = Extended Temp Blank = Commercial Temp
Package E = TSOP PA = 44-Lead PSOP TB = Ext. Temp 44-Lead PSOP Product line designator for all Intel Flash products
Density / Organization 00X = x8-only (X = 1, 2, 4, 8) X00 = x8/x16 Selectable (X = 2, 4, 8)
VALID COMBINATIONS: 40-Lead TSOP E28F004BVT60 E28F004BVB60 E28F004BVT80 E28F004BVB80 E28F004BVT120 E28F004BVB120 TE28F004BVT80 TE28F004BVB80 TE28F004BET120 TE28F004BEB120 44-Lead PSOP PA28F400BVT60 PA28F400BVB60 PA28F400BVT80 PA28F400BVB80 PA28F400BVT120 PA28F400BVB120 TB28F400BVT80 TB28F400BVB80 48-Lead TSOP E28F400CVT60 E28F400CVB60 E28F400CVT80 E28F400CVB80
Architecture B = Boot Block C = Compact 48-Lead TSOP Boot Block
0530_23
Commercial
56-Lead TSOP E28F400BVT60 E28F400BVB60 E28F400BVT80 E28F400BVB80
Extended
TE28F400CVT80 TE28F400CVB80 TE28F400CET120 TE28F400CEB120
TE28F400BVT80 TE28F400BVB80
Table 24. Summary of Line Items VCC Name 28F004BV 28F400BV 28F400CV 28F004BE 28F400CE 56 2.7V 3.3V 5V 5V VPP 12V 40-Ld 44-Ld 48-Ld 56-Ld TSOP PSOP TSOP TSOP 0C - +70C -40C - +85C
PRELIMINARY
E
Order Number 290599 292194 292154 290531 290539 292164 290448 290449 290451 290450 292148 292172 292130
4-MBIT SmartVoltage BOOT BLOCK FAMILY
APPENDIX B ADDITIONAL INFORMATION
RELATED INTEL INFORMATION(1,2)
Document
Smart 5 Boot Block Flash Memory Family 2, 4, 8 Mbit Datasheet AB-65 Migrating Designs from SmartVoltage Boot Block to Smart 5 Flash AB-60 2/4/8-Mbit SmartVoltage Boot Block Flash Memory Family 2-Mbit SmartVoltage Boot Block Flash Memory Family Datasheet 8-Mbit SmartVoltage Boot Block Flash Memory Family Datasheet AP-611 2/4M Boot Block Compatibility with 2/4/8-M SmartVoltage Boot Block Flash Memories 28F002/200BX-T/B 2-Mbit Boot Block Flash Memory Datasheet 28F002/200BL-T/B 2-Mbit Low Power Boot Block Flash Memory Datasheet 28F004/400BX-T/B 4-Mbit Boot Block Flash Memory Datasheet 28F004/400BL-T/B 4-Mbit Low Power Boot Block Flash Memory Datasheet AP-604 Using Intel's Boot Block Flash Memory Parameter Blocks to Replace EEPROM AP-617 Additional Flash Data Protection Using VPP, RP#, and WP# AB-57 Boot Block Architecture for Safe Firmware Updates
NOTES: 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. Internation customers should al contact their local Intel or distribution sales office. 2. Visit Intel's World Wide Web home page at http://www.Intel.com for technical documentation and tools.
PRELIMINARY
57

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